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公开(公告)号：US20110256681A1
公开(公告)日：2011-10-20
申请号：US13166481
申请日：2011-06-22
Applicant: Chun-Chieh Lin , Wei-Hua Hsu , Yu-En Percy Chang , Chung Li Chang , Chi-Feng Cheng , Win Hung , Kishimoto Ko
Inventor： Chun-Chieh Lin , Wei-Hua Hsu , Yu-En Percy Chang , Chung Li Chang , Chi-Feng Cheng , Win Hung , Kishimoto Ko
IPC: H01L21/336
CPC classification number: H01L29/665 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
Abstract: A method includes forming a gate stack over a semiconductor substrate, and forming a first silicon germanium (SiGe) region in the semiconductor substrate and adjacent the gate stack. The first SiGe region has a first atomic percentage of germanium to germanium and silicon. A second SiGe region is formed over the first SiGe region. The second SiGe region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is lower than the first atomic percentage, wherein the first and the second SiGe regions form a source/drain stressor of a metal-oxide-semiconductor (MOS) device.
Abstract translation: 一种方法包括在半导体衬底上形成栅叠层，并在半导体衬底中形成第一硅锗（SiGe）区，并邻近栅叠。 第一个SiGe区域具有锗与锗和硅的第一原子百分比。 在第一SiGe区域上形成第二SiGe区域。 第二SiGe区域具有锗与锗和硅的第二原子百分比。 第二原子百分比低于第一原子百分比，其中第一和第二SiGe区域形成金属氧化物半导体（MOS）器件的源极/漏极应力源。
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Patent Agency Ranking
公开(公告)号：US08569846B2
公开(公告)日：2013-10-29
申请号：US13166481
申请日：2011-06-22
Applicant: Chun-Chieh Lin , Wei-Hua Hsu , Yu-En Percy Chang , Chung Li Chang , Chi-Feng Cheng , Win Hung , Kishimoto Ko
Inventor： Chun-Chieh Lin , Wei-Hua Hsu , Yu-En Percy Chang , Chung Li Chang , Chi-Feng Cheng , Win Hung , Kishimoto Ko
IPC: H01L29/78
CPC classification number: H01L29/665 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
Abstract: A method includes forming a gate stack over a semiconductor substrate, and forming a first silicon germanium (SiGe) region in the semiconductor substrate and adjacent the gate stack. The first SiGe region has a first atomic percentage of germanium to germanium and silicon. A second SiGe region is formed over the first SiGe region. The second SiGe region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is lower than the first atomic percentage, wherein the first and the second SiGe regions form a source/drain stressor of a metal-oxide-semiconductor (MOS) device.
Abstract translation: 一种方法包括在半导体衬底上形成栅叠层，并在半导体衬底中形成第一硅锗（SiGe）区，并邻近栅叠。 第一个SiGe区域具有锗与锗和硅的第一原子百分比。 在第一SiGe区域上形成第二SiGe区域。 第二SiGe区域具有锗与锗和硅的第二原子百分比。 第二原子百分比低于第一原子百分比，其中第一和第二SiGe区域形成金属氧化物半导体（MOS）器件的源极/漏极应力源。
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公开(公告)号：US20080265256A1
公开(公告)日：2008-10-30
申请号：US11796369
申请日：2007-04-27
Applicant: Chun-Chieh Lin , Wei-Hua Hsu , Yu-En Percy Chang , Chung Li Chang , Chi-Feng Cheng , Win Hung , Kishimoto Ko
Inventor： Chun-Chieh Lin , Wei-Hua Hsu , Yu-En Percy Chang , Chung Li Chang , Chi-Feng Cheng , Win Hung , Kishimoto Ko
IPC: H01L29/94
CPC classification number: H01L29/665 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein the SiGe region has a first atomic percentage of germanium to germanium and silicon; and a silicide region over the SiGe region. The silicide region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is substantially lower than the first atomic percentage.
Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; SiGe区域，其中SiGe区域具有锗到锗和硅的第一原子百分比; 以及SiGe区域上的硅化物区域。 硅化物区域具有锗与锗和硅的第二原子百分比。 第二原子百分比基本上低于第一原子百分数。
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公开(公告)号：US07989901B2
公开(公告)日：2011-08-02
申请号：US11796369
申请日：2007-04-27
Applicant: Chun-Chieh Lin , Wei-Hua Hsu , Yu-En Percy Chang , Chung Li Chang , Chi-Feng Cheng , Win Hung , Kishimoto Ko
Inventor： Chun-Chieh Lin , Wei-Hua Hsu , Yu-En Percy Chang , Chung Li Chang , Chi-Feng Cheng , Win Hung , Kishimoto Ko
IPC: H01L29/78
CPC classification number: H01L29/665 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein the SiGe region has a first atomic percentage of germanium to germanium and silicon; and a silicide region over the SiGe region. The silicide region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is substantially lower than the first atomic percentage.
Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; SiGe区域，其中SiGe区域具有锗到锗和硅的第一原子百分比; 以及SiGe区域上的硅化物区域。 硅化物区域具有锗与锗和硅的第二原子百分比。 第二原子百分比基本上低于第一原子百分数。
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5.发明授权Method of automatically creating a semiconductor processing prober device file 有权自动创建半导体处理探测器设备文件的方法公开(公告)号：US07271609B2
公开(公告)日：2007-09-18
申请号：US10908537
申请日：2005-05-16
Applicant: Kevin Liao , Edward Chen , Win Hung , Jumbo Chuang , Chang-Chi Hsu , Chia-Ping Liu , Chun-Chieh Hsiao
Inventor： Kevin Liao , Edward Chen , Win Hung , Jumbo Chuang , Chang-Chi Hsu , Chia-Ping Liu , Chun-Chieh Hsiao
IPC: G01R31/26
CPC classification number: G01R31/2894 , G01R31/31718 , G01R31/318511
Abstract: Described is a method for automatically generating a wafer prober file whereby testing parameters and die identities can be established for testing a complete semiconductor wafer and whereby acceptable or rejected dies can be identified and correlated later with where the good or bad dies are physically located on a wafer-under-test.
Abstract translation: 描述了一种用于自动生成晶片探测器文件的方法，由此可以建立测试参数和芯片标识以测试完整的半导体晶片，并且由此可以识别和相关联的可接受的或拒绝的裸片，并将其与物理位置的物理位置 晶片未测试。
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6.发明申请Method of Automatically Creating a Semiconductor Processing Prober Device File 有权自动创建半导体处理探测器设备文件的方法公开(公告)号：US20060255824A1
公开(公告)日：2006-11-16
申请号：US10908537
申请日：2005-05-16
Applicant: Kevin Liao , Edward Chen , Win Hung , Jumbo Chuang , Chang-Chi Hsu , Chia-Ping Liu , Chun-Chieh Hsiao
Inventor： Kevin Liao , Edward Chen , Win Hung , Jumbo Chuang , Chang-Chi Hsu , Chia-Ping Liu , Chun-Chieh Hsiao
CPC classification number: G01R31/2894 , G01R31/31718 , G01R31/318511
Abstract: Described is a method for automatically generating a wafer prober file whereby testing parameters and die identities can be established for testing a complete semiconductor wafer and whereby acceptable or rejected dies can be identified and correlated later with where the good or bad dies are physically located on a wafer-under-test.
Abstract translation: 描述了一种用于自动生成晶片探测器文件的方法，由此可以建立测试参数和芯片标识以测试完整的半导体晶片，并且由此可以识别和相关联的可接受的或拒绝的裸片，并将其与物理位置的物理位置 晶片未测试。
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