发明授权
- 专利标题: High performance memory interface circuit architecture
- 专利标题(中): 高性能存储器接口电路架构
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申请号: US13614526申请日: 2012-09-13
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公开(公告)号: US08593195B1公开(公告)日: 2013-11-26
- 发明人: Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
- 申请人: Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Ward & Zinna, LLC
- 主分类号: H03H11/16
- IPC分类号: H03H11/16
摘要:
A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
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