- 专利标题: Time division multiplexed limited switch dynamic logic
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申请号: US13524562申请日: 2012-06-15
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公开(公告)号: US08604832B1公开(公告)日: 2013-12-10
- 发明人: Leland Chang , Robert K. Montoye , Yutaka Nakamura
- 申请人: Leland Chang , Robert K. Montoye , Yutaka Nakamura
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Tutunjian & Bitetto, P.C.
- 代理商 Vazken Alexanian
- 主分类号: H03K19/00
- IPC分类号: H03K19/00
摘要:
A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.
公开/授权文献
- US20130328592A1 TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC 公开/授权日:2013-12-12