发明授权
- 专利标题： FinFET parasitic capacitance reduction using air gap
- 专利标题（中）： 使用气隙对FinFET寄生电容进行减小
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申请号： US13272409申请日： 2011-10-13
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公开(公告)号： US08637930B2公开(公告)日： 2014-01-28
- 发明人: Takashi Ando , Josephine B. Chang , Sivananda K. Kanakasabapathy , Pranita Kulkarni , Theodorus E. Standaert , Tenko Yamashita
- 申请人： Takashi Ando , Josephine B. Chang , Sivananda K. Kanakasabapathy , Pranita Kulkarni , Theodorus E. Standaert , Tenko Yamashita
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Company
- 当前专利权人： International Business Machines Company
- 当前专利权人地址： US NY Armonk
- 代理机构： Harrington & Smith
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L21/336
摘要：
A transistor, for example a FinFET, includes a gate structure disposed over a substrate. The gate structure has a width and also a length and a height defining two opposing sidewalls of the gate structure. The transistor further includes at least one electrically conductive channel between a source region and a drain region that passes through the sidewalls of the gate structure; a dielectric layer disposed over the gate structure and portions of the electrically conductive channel that are external to the gate structure; and an air gap underlying the dielectric layer. The air gap is disposed adjacent to the sidewalls of the gate structure and functions to reduce parasitic capacitance of the transistor. At least one method to fabricate the transistor is also disclosed.
公开/授权文献
- US20130093019A1 FINFET PARASITIC CAPACITANCE REDUCTION USING AIR GAP 公开/授权日：2013-04-18
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