发明授权
US08640005B2 Method and apparatus for using cache memory in a system that supports a low power state
有权
在支持低功率状态的系统中使用高速缓冲存储器的方法和装置
- 专利标题: Method and apparatus for using cache memory in a system that supports a low power state
- 专利标题(中): 在支持低功率状态的系统中使用高速缓冲存储器的方法和装置
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申请号: US12785182申请日: 2010-05-21
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公开(公告)号: US08640005B2公开(公告)日: 2014-01-28
- 发明人: Christopher B. Wilkerson , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
- 申请人: Christopher B. Wilkerson , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Trop, Pruner & Hu, P.C.
- 主分类号: G11C29/00
- IPC分类号: G11C29/00
摘要:
A cache memory system uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. In an embodiment, error correction logic may include a first error correction logic to determine a number of errors in data that is stored in a cache line of a cache memory, and a second error correction logic to receive the data from the first error correction logic if the number of errors is determined to be greater than one and to perform error correction responsive to receipt of the data. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state. Other embodiments are described and claimed.