发明授权
- 专利标题： Method of making chip-on-lead package
- 专利标题（中）： 芯片引线封装方法
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申请号： US12727258申请日： 2010-03-19
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公开(公告)号： US08642395B2公开(公告)日： 2014-02-04
- 发明人: Zhe Li , Qingchun He , Guanhua Wang , Zhijie Wang , Nan Xu
- 申请人： Zhe Li , Qingchun He , Guanhua Wang , Zhijie Wang , Nan Xu
- 申请人地址： US TX Austin
- 专利权人： Freescale Semiconductor, Inc.
- 当前专利权人： Freescale Semiconductor, Inc.
- 当前专利权人地址： US TX Austin
- 代理商 Charles Bergere
- 优先权： CN200910130250 20090330
- 主分类号： H01L21/60
- IPC分类号： H01L21/60 ; H01L21/56 ; H01L33/62
摘要：
A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided.
公开/授权文献
- US20100248426A1 METHOD OF MAKING CHIP-ON-LEAD PACKAGE 公开/授权日：2010-09-30
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