发明授权
US08650385B2 Instruction fetch apparatus, processor and program counter addition control method
有权
指令提取装置,处理器和程序计数器附加控制方法
- 专利标题: Instruction fetch apparatus, processor and program counter addition control method
- 专利标题(中): 指令提取装置,处理器和程序计数器附加控制方法
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申请号: US13024580申请日: 2011-02-10
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公开(公告)号: US08650385B2公开(公告)日: 2014-02-11
- 发明人: Hitoshi Kai , Hiroaki Sakaguchi , Hiroshi Kobayashi , Katsuhiko Metsugi , Haruhisa Yamamoto , Yousuke Morita , Koichi Hasegawa , Taichi Hirao
- 申请人: Hitoshi Kai , Hiroaki Sakaguchi , Hiroshi Kobayashi , Katsuhiko Metsugi , Haruhisa Yamamoto , Yousuke Morita , Koichi Hasegawa , Taichi Hirao
- 申请人地址: JP Tokyo
- 专利权人: Sony Corporation
- 当前专利权人: Sony Corporation
- 当前专利权人地址: JP Tokyo
- 代理机构: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- 优先权: JP2010-075782 20100329
- 主分类号: G06F9/30
- IPC分类号: G06F9/30 ; G06F9/40 ; G06F15/00
摘要:
An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially; a change designation register configured to designate a change of an increment value on the program counter; an increment value register configured to hold the changed increment value; and an addition control section configured such that if the change designation register designates the change of the increment value on the program counter, then the addition control section increments the program counter based on the changed increment value held in the increment value register, the addition control section further incrementing the program counter by an instruction word length if the change designation register does not designate any change of the increment value on the program counter.
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