Cache memory and cache memory control unit
    1.
    发明授权
    Cache memory and cache memory control unit 有权
    缓存内存和缓存内存控制单元

    公开(公告)号:US09535841B2

    公开(公告)日:2017-01-03

    申请号:US13515315

    申请日:2010-12-14

    IPC分类号: G06F13/00 G06F12/08

    摘要: Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.

    摘要翻译: 在包括共享高速缓冲存储器的多处理器中有效地执行处理器之间的数据传输。 除了标签地址字段221,有效字段222和脏字段223之外,高速缓冲存储器的标签存储部分220中的每个条目保存参考数字段224.参考号字段224被设置在数据写入中, 并且其值在每次读取访问之后递减。 当参考号字段224的值从“1”改变为“0”时,该条目无效而不执行回写操作。 当高速缓冲存储器用于多处理器系统中的处理器之间的通信时,高速缓冲存储器用作共享FIFO,并且使用的数据被自动删除。

    Method for producing electrolyte solution for lithium ion battery and battery using same
    3.
    发明授权
    Method for producing electrolyte solution for lithium ion battery and battery using same 有权
    锂离子电池用电解液的制造方法及其使用方法

    公开(公告)号:US08097360B2

    公开(公告)日:2012-01-17

    申请号:US11911901

    申请日:2006-04-10

    IPC分类号: H01M6/04

    摘要: A method for producing an electrolyte solution for a lithium ion battery involving reacting a lithium halide selected from the group consisting of lithium fluoride, lithium chloride, lithium bromide, lithium iodide and a mixture of at least two of these, with phosphorus pentachloride and hydrogen fluoride in a nonaqueous organic solvent, thereby producing lithium hexafluorophosphate as an electrolyte of the electrolyte solution.

    摘要翻译: 一种锂离子电池用电解液的制造方法,其特征在于,使选自由氟化锂,氯化锂,溴化锂,碘化锂及其中的至少两种的混合物构成的组中的卤化锂与五氯化磷和氟化氢反应 在非水有机溶剂中,由此生产六氟磷酸锂作为电解质溶液的电解质。

    INSTRUCTION FETCH APPARATUS, PROCESSOR AND PROGRAM COUNTER ADDITION CONTROL METHOD
    4.
    发明申请
    INSTRUCTION FETCH APPARATUS, PROCESSOR AND PROGRAM COUNTER ADDITION CONTROL METHOD 有权
    指令设备,处理器和程序计数器附加控制方法

    公开(公告)号:US20110238952A1

    公开(公告)日:2011-09-29

    申请号:US13024580

    申请日:2011-02-10

    IPC分类号: G06F9/38

    摘要: An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially; a change designation register configured to designate a change of an increment value on the program counter; an increment value register configured to hold the changed increment value; and an addition control section configured such that if the change designation register designates the change of the increment value on the program counter, then the addition control section increments the program counter based on the changed increment value held in the increment value register, the addition control section further incrementing the program counter by an instruction word length if the change designation register does not designate any change of the increment value on the program counter.

    摘要翻译: 一种提取指令装置,其特征在于包括:程序计数器,被配置为在其中顺序放置属于多个指令序列的指令的程序中管理目标要执行的指令的地址; 变更指定寄存器,被配置为指定所述程序计数器上的增量值的变化; 增量值寄存器,被配置为保持所述改变的增量值; 以及附加控制部分,其被配置为使得如果所述改变指定寄存器指定所述程序计数器上的所述增量值的改变,则所述相加控制部分基于所述增量值寄存器中保持的改变的增量值来增加所述程序计数器,所述加法控制 如果改变指定寄存器没有指定程序计数器上的增量值的任何改变,则进一步将程序计数器递增指令字长度。

    Floating-point number arithmetic circuit for handling immediate values
    5.
    发明授权
    Floating-point number arithmetic circuit for handling immediate values 有权
    用于处理立即值的浮点数算术电路

    公开(公告)号:US07949696B2

    公开(公告)日:2011-05-24

    申请号:US11280244

    申请日:2005-11-17

    IPC分类号: G06F7/00 G06F7/38 G06F9/30

    摘要: Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-point number arithmetic operation on a floating-point number of a predetermined precision, and a converting circuit for converting data into the floating-point number of predetermined precision and supplying the floating-point number of the predetermined precision to at least either one of input terminals of the floating-point number arithmetic unit.

    摘要翻译: 这里公开了一种用于有效地提供要进行的算术运算的数据的浮点数运算电路。 浮点数算术电路包括用于对预定精度的浮点数执行预定的浮点数算术运算的浮点数运算单元和用于将数据转换为浮点数运算的浮点数运算单元 预定精度,并将预定精度的浮点数提供给浮点数运算单元的输入端中的至少一个。

    Arithmetic decoding device
    6.
    发明授权
    Arithmetic decoding device 有权
    算术解码装置

    公开(公告)号:US07884743B2

    公开(公告)日:2011-02-08

    申请号:US12431828

    申请日:2009-04-29

    IPC分类号: H03M7/00

    摘要: Disclosed herein is an arithmetic decoding device including: an arithmetic decoding unit configured to decode coded data resulting from arithmetic coding on a basis of a context variable indicating a probability state and a most probable symbol; a plurality of arithmetic registers configured to supply the context variable to the arithmetic decoding unit and retain a result of operation by the arithmetic decoding unit; and a plurality of save registers configured to save contents retained in the arithmetic registers.

    摘要翻译: 本文公开了一种算术解码装置,包括:算术解码单元,被配置为基于指示概率状态的上下文变量和最可能的符号来解码由算术编码产生的编码数据; 多个算术寄存器,被配置为将所述上下文变量提供给所述算术解码单元,并且保留所述算术解码单元的操作结果; 以及多个保存寄存器,被配置为保存保留在算术寄存器中的内容。

    Arithmetic decoding apparatus
    7.
    发明授权
    Arithmetic decoding apparatus 失效
    算术解码装置

    公开(公告)号:US07821430B2

    公开(公告)日:2010-10-26

    申请号:US12394132

    申请日:2009-02-27

    申请人: Hiroaki Sakaguchi

    发明人: Hiroaki Sakaguchi

    IPC分类号: H03M7/30

    CPC分类号: H03M7/4006

    摘要: Disclosed herein is an arithmetic decoding apparatus that decodes encoded data while updating first and second state variables based on first and second context variables. The first context variable represents a probability state. The second context variable represents a most probable symbol. The arithmetic decoding apparatus includes: a decoding information table that stores transitions of a range of the most probable symbol and a range of a least probable symbol within a range identified by the first context variable, and a number of a symbol for which the range of the most probable symbol becomes less than a specific value; a number-of-symbols determination section configured to determine the number of symbols in the encoded data that are to be decoded collectively; and an output section configured to decode and output a symbol corresponding to the number of symbols that are to be decoded collectively.

    摘要翻译: 这里公开了一种在基于第一和第二上下文变量更新第一和第二状态变量的同时对编码数据进行解码的算术解码装置。 第一个上下文变量表示概率状态。 第二个上下文变量表示最可能的符号。 算术解码装置包括:解码信息表,其存储最可能符号的范围的转变和由第一上下文变量所标识的范围内的最不可能符号的范围,以及符号的数量, 最可能的符号变得小于特定值; 符号数确定部,被配置为确定要被集体解码的编码数据中的符号数; 以及输出部,被配置为解码并输出与要被集体解码的符号的数量相对应的符号。

    ARITHMETIC DECODING APPARATUS
    8.
    发明申请
    ARITHMETIC DECODING APPARATUS 有权
    算术解码设备

    公开(公告)号:US20100134330A1

    公开(公告)日:2010-06-03

    申请号:US12625630

    申请日:2009-11-25

    申请人: Hiroaki SAKAGUCHI

    发明人: Hiroaki SAKAGUCHI

    IPC分类号: H03M7/34

    摘要: Disclosed herein is an arithmetic decoding apparatus including an instruction decoder configured to decode an arithmetically encoded data decoding instruction to be executed for carrying out an arithmetic-decoding process of arithmetically decoding arithmetically encoded data into a binary signal; an execution condition code holding section configured to hold the binary signal obtained as a result of an immediately preceding arithmetic-decoding process as an execution condition code; and an arithmetic decoding execution section configured to determine whether a context number specified by the arithmetically encoded data decoding instruction is to be used as a context index as it is or the specified context number incremented by 1 is to be used as the context index in accordance with the execution condition code, and carry out the arithmetic decoding process by making use of the determined context index.

    摘要翻译: 本文公开了一种算术解码装置,包括指令解码器,其被配置为对要执行的算术编码数据解码指令进行解码,以执行将算术编码数据算术解码为二进制信号的算术解码处理; 执行条件码保持部,被配置为将作为紧接在前的算术解码处理的结果获得的二进制信号保持为执行条件码; 以及算术解码执行部,被配置为确定由算术编码的数据解码指令指定的上下文编号是否按原样用作上下文索引,或者按照递增1的指定上下文编号被用作上下文索引 利用执行条件代码,并且通过利用所确定的上下文索引来执行算术解码处理。

    Method for producing sulfonimide or its salt
    10.
    发明授权
    Method for producing sulfonimide or its salt 有权
    制备磺酰亚胺或其盐的方法

    公开(公告)号:US06252111B1

    公开(公告)日:2001-06-26

    申请号:US09504113

    申请日:2000-02-15

    IPC分类号: C07C30334

    CPC分类号: C07C303/40 C07C311/48

    摘要: The invention relates to a method for producing a sulfonimide or its alkali metal salt. The method includes the steps of (a) reacting a precursory salt of the sulfonimide with a base contained in a basic aqueous solution, thereby producing a first aqueous solution containing the alkali metal salt and an amine; (b) removing the amine from the first aqueous solution to obtain a second aqueous solution containing the alkali metal salt; and (c) crystallizing the alkali metal salt in the second aqueous solution. The base is potassium hydroxide, sodium hydroxide or lithium hydroxide. The base is added to the second aqueous solution to generate the crystallization. The precursory salt is formed when the sulfonimide is reacted with a tertiary amine or a heterocyclic amine. The alkali metal salt is produced easily and economically in an industrial scale production with high purity and high yield.

    摘要翻译: 本发明涉及磺酰亚胺或其碱金属盐的制备方法。 该方法包括以下步骤:(a)将磺酰亚胺的前体盐与碱性水溶液中所含的碱反应,由此制备含有碱金属盐和胺的第一水溶液; (b)从第一水溶液中除去胺,得到含有碱金属盐的第二水溶液; 和(c)使第二水溶液中的碱金属盐结晶。 碱是氢氧化钾,氢氧化钠或氢氧化锂。 将碱加入到第二水溶液中以产生结晶。 当磺酰亚胺与叔胺或杂环胺反应时,形成前体盐。 碱金属盐在高纯度和高产率的工业规模生产中容易且经济地生产。