Invention Grant
- Patent Title: Flash memory with nano-pillar charge trap
- Patent Title (中): 闪存与纳米柱电荷陷阱
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Application No.: US12623369Application Date: 2009-11-20
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Publication No.: US08687418B1Publication Date: 2014-04-01
- Inventor: Rajiv Yadav Ranjan , Ebrahim Abedifard , Petro Estakhri , Parviz Keshtbod
- Applicant: Rajiv Yadav Ranjan , Ebrahim Abedifard , Petro Estakhri , Parviz Keshtbod
- Applicant Address: US CA Fremont
- Assignee: Avalanche Technology, Inc.
- Current Assignee: Avalanche Technology, Inc.
- Current Assignee Address: US CA Fremont
- Agency: IPxLaw Group LLP
- Agent Maryam Imam
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
An embodiment of the present invention includes a non-volatile storage unit comprising a first and second N-diffusion well separated by a distance of P-substrate. A first isolation layer is formed upon the first and second N-diffusion wells and the P-substrate. A nano-pillar charge trap layer is formed upon the first isolation layer and includes conductive nano-pillars interspersed between non-conducting regions. The storage unit further includes a second isolation layer formed upon the nano-pillar charge trap layer; and at least one word line formed upon the second isolation layer and above a region of nano-pillar charge trap layer. The nano-pillar charge trap layer is operative to trap charge upon application of a threshold voltage. Subsequently, the charge trap layer may be read to determine any charge stored in the non-volatile storage unit, where presence or absence of stored charge in the charge trap layer corresponds to a bit value.
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