发明授权
US08742554B2 Circuit member, manufacturing method for circuit members, semiconductor device, and surface lamination structure for circuit member
有权
电路部件，电路部件的制造方法，半导体装置以及电路部件的表面层叠结构
- 专利标题： Circuit member, manufacturing method for circuit members, semiconductor device, and surface lamination structure for circuit member
- 专利标题（中）： 电路部件，电路部件的制造方法，半导体装置以及电路部件的表面层叠结构
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申请号： US11912163申请日： 2006-04-26
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公开(公告)号： US08742554B2公开(公告)日： 2014-06-03
- 发明人: Yo Shimazaki , Hiroyuki Saito , Masachika Masuda , Kenji Matsumura , Masaru Fukuchi , Takao Ikezawa
- 申请人： Yo Shimazaki , Hiroyuki Saito , Masachika Masuda , Kenji Matsumura , Masaru Fukuchi , Takao Ikezawa
- 申请人地址： JP Shinjuku-Ku
- 专利权人： Dai Nippon Printing Co., Ltd.
- 当前专利权人： Dai Nippon Printing Co., Ltd.
- 当前专利权人地址： JP Shinjuku-Ku
- 代理机构： Burr & Brown, PLLC
- 优先权： JP2005-128259 20050426
- 国际申请： PCT/JP2006/308721 WO 20060426
- 国际公布： WO2006/115267 WO 20061102
- 主分类号： H01L23/495
- IPC分类号： H01L23/495
摘要：
A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.
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