Invention Grant
- Patent Title: Enhanced dislocation stress transistor
- Patent Title (中): 增强位错应力晶体管
-
Application No.: US12191814Application Date: 2008-08-14
-
Publication No.: US08779477B2Publication Date: 2014-07-15
- Inventor: Cory Weber , Mark Liu , Anand Murthy , Hemant Deshpande , Daniel B. Aubertine
- Applicant: Cory Weber , Mark Liu , Anand Murthy , Hemant Deshpande , Daniel B. Aubertine
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle, PLLC
- Main IPC: H01L29/76
- IPC: H01L29/76
Abstract:
A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
Public/Granted literature
- US20100038685A1 ENHANCED DISLOCATION STRESS TRANSISTOR Public/Granted day:2010-02-18
Information query
IPC分类:
