公开(公告)号：US20100038685A1

公开(公告)日：2010-02-18

申请号：US12191814

申请日：2008-08-14

申请人： Cory Weber ,  Mark Liu ,  Anand Murthy ,  Hemant Deshpande ,  Daniel B. Aubertine

发明人： Cory Weber ,  Mark Liu ,  Anand Murthy ,  Hemant Deshpande ,  Daniel B. Aubertine

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

摘要： A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

摘要翻译： 提供了一种设备。 该器件包括形成在半导体衬底上的晶体管，该晶体管具有导通沟道。 该器件包括与半导体衬底上的导电沟道相邻形成的至少一个边缘位错。 该装置还包括在导电通道之上引入的至少一个自由表面和至少一个边缘错位。

公开(公告)号：US20140284626A1

公开(公告)日：2014-09-25

申请号：US14297847

申请日：2014-06-06

申请人： Cory Weber ,  Mark Liu ,  Anand Murthy ,  Hemant Deshpande ,  Daniel B. Aubertine

发明人： Cory Weber ,  Mark Liu ,  Anand Murthy ,  Hemant Deshpande ,  Daniel B. Aubertine

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

摘要： A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

摘要翻译： 提供了一种设备。 该器件包括形成在半导体衬底上的晶体管，该晶体管具有导通通道。 该器件包括与半导体衬底上的导电沟道相邻形成的至少一个边缘位错。 该装置还包括在导电通道之上引入的至少一个自由表面和至少一个边缘错位。

公开(公告)号：US08779477B2

公开(公告)日：2014-07-15

申请号：US12191814

申请日：2008-08-14

申请人： Cory Weber ,  Mark Liu ,  Anand Murthy ,  Hemant Deshpande ,  Daniel B. Aubertine

发明人： Cory Weber ,  Mark Liu ,  Anand Murthy ,  Hemant Deshpande ,  Daniel B. Aubertine

IPC分类号： H01L29/76

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

摘要： A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

摘要翻译： 提供了一种设备。 该器件包括形成在半导体衬底上的晶体管，该晶体管具有导通沟道。 该器件包括与半导体衬底上的导电沟道相邻形成的至少一个边缘位错。 该装置还包括在导电通道之上引入的至少一个自由表面和至少一个边缘错位。

公开(公告)号：US20090321838A1

公开(公告)日：2009-12-31

申请号：US12215989

申请日：2008-06-30

申请人： Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel B. Aubertine

发明人： Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel B. Aubertine

IPC分类号： H01L29/423 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L29/66628 ,  H01L29/7834

摘要： A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.

摘要翻译： CMOS器件包括NMOS（110）和PMOS（130）晶体管，每个晶体管包括限定栅极绝缘体平面（150,170）的栅电极（111,131）和栅极绝缘体（112,132）。 晶体管每个还包括具有栅极绝缘体平面下方的第一部分（115,135）和栅极绝缘体平面上方的第二部分（116,136）的源/漏区（113/114,133 / 134） 绝缘材料（117）。 NMOS晶体管还包括阻挡层（121），其具有在栅电极和源极触点（118）之间的部分（122）和栅极电极和漏极触点（119）之间的部分（123）。 所述PMOS晶体管还包括阻挡层（141），所述阻挡层（141）具有在所述源极区域和所述绝缘材料之间的部分（142）以及所述漏极区域和所述绝缘材料之间的部分（143）。

公开(公告)号：US07663192B2

公开(公告)日：2010-02-16

申请号：US12215989

申请日：2008-06-30

申请人： Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel Aubertine

发明人： Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel Aubertine

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L29/66628 ,  H01L29/7834

摘要： A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.

摘要翻译： CMOS器件包括NMOS（110）和PMOS（130）晶体管，每个晶体管包括限定栅极绝缘体平面（150,170）的栅电极（111,131）和栅极绝缘体（112,132）。 晶体管每个还包括具有栅极绝缘体平面下方的第一部分（115,135）和栅极绝缘体平面上方的第二部分（116,136）的源/漏区（113/114,133 / 134） 绝缘材料（117）。 NMOS晶体管还包括阻挡层（121），其具有在栅电极和源极触点（118）之间的部分（122）和栅极电极和漏极触点（119）之间的部分（123）。 所述PMOS晶体管还包括阻挡层（141），所述阻挡层（141）具有在所述源极区域和所述绝缘材料之间的部分（142）以及所述漏极区域和所述绝缘材料之间的部分（143）。

公开(公告)号：US20210202378A1

公开(公告)日：2021-07-01

申请号：US16728887

申请日：2019-12-27

申请人： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

发明人： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC分类号： H01L23/522 ,  H01L27/12 ,  H01L21/762 ,  H01L21/768

摘要： A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US20130153965A1

公开(公告)日：2013-06-20

申请号：US13764675

申请日：2013-02-11

申请人： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

发明人： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

IPC分类号： H01L29/78

CPC分类号： H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

摘要： Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

摘要翻译： 本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变 硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历 由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。

公开(公告)号：US08373154B2

公开(公告)日：2013-02-12

申请号：US12609711

申请日：2009-10-30

申请人： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

发明人： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

IPC分类号： H01L29/08 ,  H01L31/0312 ,  H01L29/12 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

摘要： Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

公开(公告)号：US08154087B2

公开(公告)日：2012-04-10

申请号：US13107739

申请日：2011-05-13

申请人： Ted E. Cook, Jr. ,  Bernhard Sell ,  Anand Murthy

发明人： Ted E. Cook, Jr. ,  Bernhard Sell ,  Anand Murthy

IPC分类号： H01L27/088

CPC分类号： H01L29/7848 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834

摘要： A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.

摘要翻译： 描述了多组分应变诱导半导体区域。 在一个实施方案中，在与晶体衬底横向相邻的这种应变诱导半导体区域的形成导致赋予晶体衬底的单轴应变，从而提供应变晶体衬底。 在一个实施例中，多组分应变诱导材料区域包括由界面分离的第一部分和第二部分。 在具体实施方案中，两部分的电荷 - 载流子掺杂剂杂质原子的浓度在界面处彼此不同。

公开(公告)号：US07968957B2

公开(公告)日：2011-06-28

申请号：US12893983

申请日：2010-09-29

申请人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

发明人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

IPC分类号： H01L21/00

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

摘要翻译： 本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料 在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。