Techniques are described for constructing maximum transition run (MTR) modulation code based upon a multi-level (ML) run-length limited (RLL) finite state machine (FSM) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (HDD) via a read channel and recover data from the HDD using MTR modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct an MTR modulation code to mimic the optimized Markov source based upon an FSM having a limited transition run length and a multi-level periodic structure. The FSM provides at least two different sets of penalties in a period.