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    Fixed-point processing using quantization levels based on floating-point processing
    2.
    发明授权
    Fixed-point processing using quantization levels based on floating-point processing 有权
    使用基于浮点处理的量化级的定点处理

    公开(公告)号：US08743493B1

    公开(公告)日：2014-06-03

    申请号：US13742753

    申请日：2013-01-16

    申请人： LSI Corporation

    发明人： Wu Chang ,  Fan Zhang ,  Ming Jin

    IPC分类号： G11B20/10

    CPC分类号： G11B20/10268

    摘要： An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry comprises a detector and a decoder coupled to the detector. The detector is configured to perform fixed-point detection on a digital data signal using a first set of quantization levels determined based at least in part on a result of a floating-point detection of the digital data signal. The decoder is configured to perform fixed-point decoding on an output of the detector using a second set of quantization levels determined based at least in part on a result of a floating-point decoding of the output of the detector.

    摘要翻译： 一种装置包括读通道电路和与读通道电路相关联的信号处理电路。 信号处理电路包括耦合到检测器的检测器和解码器。 检测器被配置为使用至少部分地基于数字数据信号的浮点检测的结果确定的第一组量化级对数字数据信号执行定点检测。 解码器被配置为使用至少部分地基于检测器的输出的浮点解码的结果确定的第二组量化级对检测器的输出执行定点解码。

    MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE WITH MULTI-PENALTY
    3.
    发明申请
    MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE WITH MULTI-PENALTY 有权
    多级跑步有限公司有限公司有限责任公司

    公开(公告)号：US20140115381A1

    公开(公告)日：2014-04-24

    申请号：US13654931

    申请日：2012-10-18

    申请人： LSI CORPORATION

    发明人： Wu Chang ,  Razmik Karabed ,  Fan Zhang

    IPC分类号： G06F11/16 ,  G06G7/62

    CPC分类号： G11B20/1833 ,  G11B20/10277 ,  G11B20/10287

    摘要： Techniques are described for constructing maximum transition run (MTR) modulation code based upon a multi-level (ML) run-length limited (RLL) finite state machine (FSM) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (HDD) via a read channel and recover data from the HDD using MTR modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct an MTR modulation code to mimic the optimized Markov source based upon an FSM having a limited transition run length and a multi-level periodic structure. The FSM provides at least two different sets of penalties in a period.

    摘要翻译： 描述了基于实现不同处罚集的多级（ML）游程限制（RLL）有限状态机（FSM）来构建最大过渡运行（MTR）调制码的技术。 处理器被配置为经由读通道从硬盘驱动器（HDD）接收信息，并且使用MTR调制码从HDD恢复数据。 存储器具有被配置为由处理器执行以将磁记录通道建模为部分响应通道的计算机可执行指令，将信息源建模到磁记录通道以提供优化的马尔可夫源，并构建MTR调制码以模拟 基于具有有限转换行程长度和多级周期结构的FSM的优化马尔可夫源。 FSM在一段时间内至少提供两套不同的罚则。

    Iterative decoding using adaptive feedback
    4.
    发明授权
    Iterative decoding using adaptive feedback 有权
    使用自适应反馈的迭代解码

    公开(公告)号：US08687310B1

    公开(公告)日：2014-04-01

    申请号：US13687688

    申请日：2012-11-28

    申请人： LSI Corporation

    发明人： Fan Zhang ,  Jun Xiao ,  Wu Chang

    IPC分类号： G11B5/035

    CPC分类号： G11B20/10361 ,  G11B20/10268

    摘要： An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry is configured to: equalize a digital data signal; align the equalized digital data signal; determine a detector reliability metric based at least in part on the aligned equalized digital data signal; perform an iterative decoding process to determine a decoded digital data signal using the detector reliability metric; adjust the aligned equalized digital data signal using the decoded digital data signal; and repeat at least determining the detector reliability metric and performing the iterative decoding process using the adjusted equalized digital data signal.

    摘要翻译： 一种装置包括读通道电路和与读通道电路相关联的信号处理电路。 信号处理电路被配置为：均衡数字数据信号; 对齐均衡的数字数据信号; 至少部分地基于对准的均衡数字数据信号确定检测器可靠性度量; 执行迭代解码处理以使用检测器可靠性度量来确定解码的数字数据信号; 使用解码的数字数据信号调整对准的均衡数字数据信号; 并重复至少确定检测器可靠性度量并使用经调整的均衡数字数据信号执行迭代解码处理。

    Multi-Level Enumerative Encoder And Decoder
    5.
    发明申请
    Multi-Level Enumerative Encoder And Decoder 有权
    多级枚举编码器和解码器

    公开(公告)号：US20150380050A1

    公开(公告)日：2015-12-31

    申请号：US14318665

    申请日：2014-06-29

    申请人： LSI Corporation

    发明人： Victor Krachkovsky ,  Razmik Karabed ,  Shaohua Yang ,  Wu Chang

    IPC分类号： G11B20/12

    CPC分类号： G11B20/1217 ,  G11B20/1833 ,  H03M7/4006 ,  H03M13/1102

    摘要： A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level enumerative encoder operable to encode the data set before it is written to the storage medium as encoded data, wherein the enumerative encoder applies an enumeration using a plurality of level-dependent bases, and a decoder operable to decode the data set after it is read from the storage medium.

    摘要翻译： 存储系统包括可操作以保持数据集的存储介质，可操作以将数据集写入存储介质并从存储介质读取数据集的读/写头组件，可操作以编码的多级枚举编码器 其前的数据集作为编码数据被写入存储介质，其中该枚举编码器使用多个依赖于水平的基站来应用枚举，以及解码器，用于在从存储介质读取数据集之后对其进行解码。

    Systems and methods for enhanced local iteration randomization in a data decoder
    6.
    发明授权
    Systems and methods for enhanced local iteration randomization in a data decoder 有权
    用于数据解码器中增强的局部迭代随机化的系统和方法

    公开(公告)号：US09112531B2

    公开(公告)日：2015-08-18

    申请号：US13652012

    申请日：2012-10-15

    申请人： LSI Corporation

    发明人： Fan Zhang ,  Wu Chang ,  Shaohua Yang ,  Ming Jin

    IPC分类号： H03M13/05 ,  H03M13/00 ,  H03M13/11 ,  H03M13/41

    CPC分类号： H03M13/1128 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1142 ,  H03M13/41 ,  H03M13/6331 ,  H03M13/6343

    摘要： Systems and methods for data processing particularly related local iteration randomization in a data decoding circuit. In some cases a data processing system may include: a layered data decoding circuit, a value generator circuit, and a selector circuit. The layered data decoding circuit is configured to iteratively apply a data decoding algorithm up to a selected number of times to a decoder input to yield a decoded output in accordance with a layer order. The value generator circuit is operable configured to generate an adjusted number of times where the adjusted number of times is less than a default number of times. The selector circuit is operable configured to select one of the default number of times and the adjusted number of times as the selected number of times.

    摘要翻译： 用于数据处理的系统和方法特别涉及数据解码电路中的局部迭代随机化。 在一些情况下，数据处理系统可以包括：分层数据解码电路，值产生器电路和选择器电路。 分层数据解码电路被配置为将数据解码算法迭代地应用到解码器输入的选定次数，以根据层次顺序产生解码的输出。 值产生器电路可操作地配置为产生经调整次数小于默认次数的调整次数。 选择器电路可操作地配置为选择默认次数和调整次数中的一个作为所选次数。

    Encoder and decoder generation by state-splitting of directed graph
    8.
    发明授权
    Encoder and decoder generation by state-splitting of directed graph 有权
    通过有向图的状态分割生成编码器和解码器

    公开(公告)号：US09003263B2

    公开(公告)日：2015-04-07

    申请号：US13742340

    申请日：2013-01-15

    申请人： LSI Corporation

    发明人： Razmik Karabed ,  Shaohua Yang ,  Wu Chang ,  Victor Krachkovsky

    IPC分类号： G11C29/00 ,  G06F11/14 ,  G11C11/56 ,  G11C11/26

    CPC分类号： G06F11/14 ,  G11B20/1833 ,  G11C11/26 ,  G11C11/5628 ,  G11C11/5642 ,  H03M5/145

    摘要： A method of generating a hardware encoder includes generating a first directed graph characterizing a constraint set for a constrained system, identifying a scaling factor for an approximate eigenvector for the first directed graph, applying the scaling factor to the approximate eigenvector for the first directed graph to yield a scaled approximate eigenvector, partitioning arcs between each pair of states in the first directed graph, performing a state splitting operation on the first directed graph according to the partitioning of the arcs to yield a second directed graph, and generating the hardware encoder based on the second directed graph.

    摘要翻译： 生成硬件编码器的方法包括：生成表征约束系统的约束集的第一有向图，识别第一有向图的近似特征向量的缩放因子，将缩放因子应用于第一有向图的近似特征向量 产生缩放的近似特征向量，在第一有向图中的每对状态之间划分弧，根据弧的划分对第一有向图执行状态分割操作以产生第二有向图，并且基于 第二个有向图。

    Sync mark detection using branch metrics from data detector
    9.
    发明授权
    Sync mark detection using branch metrics from data detector 有权
    使用来自数据检测器的分支度量进行同步标记检测

    公开(公告)号：US08810943B2

    公开(公告)日：2014-08-19

    申请号：US13728443

    申请日：2012-12-27

    申请人： LSI Corporation

    发明人： Shaohua Yang ,  Yoon L. Liow ,  Wu Chang ,  Xuebin Wu

    IPC分类号： G11B5/09

    CPC分类号： G11B20/10222

    摘要： Methods and apparatus are provided for detecting a sync mark in a storage system, such as a hard disk drive. A sync mark is detected in a storage system by obtaining one or more branch metrics from a data detector in the storage system; generating one or more sync mark metrics using the one or more branch metrics from the data detector; and identifying the sync mark based on the sync mark metrics. An input data set is optionally compared with a plurality of portions of a sync mark pattern to yield corresponding comparison values and the comparison values can be summed to obtain at least one result. A sync mark found signal is asserted based upon the at least one result.

    摘要翻译： 提供了用于检测诸如硬盘驱动器的存储系统中的同步标记的方法和装置。 在存储系统中通过从存储系统中的数据检测器获得一个或多个分支度量来检测同步标记; 使用来自所述数据检测器的所述一个或多个分支度量来生成一个或多个同步标记度量; 以及基于同步标记度量识别同步标记。 输入数据组可选地与同步标记图案的多个部分进行比较以产生对应的比较值，并且可以将比较值相加以获得至少一个结果。 基于至少一个结果来确定发现同步标记信号。