发明授权
US08802495B2 Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
有权
半导体封装，其制造方法以及包括该半导体封装的半导体封装结构
- 专利标题： Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
- 专利标题（中）： 半导体封装，其制造方法以及包括该半导体封装的半导体封装结构
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申请号： US13955259申请日： 2013-07-31
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公开(公告)号： US08802495B2公开(公告)日： 2014-08-12
- 发明人: Ji Hwang Kim , Tae Hong Min , Chajea Jo , Taeje Cho , Young Kun Jee , Yun Seok Choi
- 申请人： Samsung Electronics Co., Ltd.
- 申请人地址： KR Gyeonggi-Do
- 专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人地址： KR Gyeonggi-Do
- 代理机构： Harness, Dickey & Pierce, P.L.C.
- 优先权： KR10-2012-0085396 20120803
- 主分类号： H01L21/50
- IPC分类号： H01L21/50 ; H01L21/56
摘要：
A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.