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    Semiconductor package and method of fabricating the same
    3.
    发明授权
    Semiconductor package and method of fabricating the same 有权

    公开(公告)号：US10734367B2

    公开(公告)日：2020-08-04

    申请号：US16232159

    申请日：2018-12-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seung-Kwan Ryu ,  Yonghwan Kwon ,  Yun Seok Choi ,  Chajea Jo ,  Taeje Cho

    IPC: H01L25/10 ,  H01L23/00 ,  H01L25/03 ,  H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

    Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

    Semiconductor package
    5.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11626385B2

    公开(公告)日：2023-04-11

    申请号：US17178327

    申请日：2021-02-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Namhoon Kim ,  Chajea Jo ,  Ohguk Kwon ,  Hyoeun Kim ,  Seunghoon Yeon

    IPC: H01L25/065 ,  H01L23/00

    Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

    Semiconductor package
    6.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11444060B2

    公开(公告)日：2022-09-13

    申请号：US16742341

    申请日：2020-01-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanguk Han ,  Chajea Jo ,  Hyoeun Kim ,  Sunkyoung Seo

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

    Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.

    Semiconductor devices having through-electrodes and methods for fabricating the same
    10.
    发明授权
    Semiconductor devices having through-electrodes and methods for fabricating the same 有权
    具有贯通电极的半导体装置及其制造方法

    公开(公告)号：US09355961B2

    公开(公告)日：2016-05-31

    申请号：US14470366

    申请日：2014-08-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chajea Jo ,  Taeje Cho ,  Hyunsoo Chung

    IPC: H01L23/538 ,  H01L21/768 ,  H01L25/065 ,  H01L23/48

    CPC classification number: H01L23/5384 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: A semiconductor device having through-electrodes and methods for fabricating the same are provided. The semiconductor device may include a first semiconductor chip including a first active surface on which a first top pad is provided; a second semiconductor chip including a second active surface on which a second top pad is provided and a second inactive surface on which a second bottom pad is provided, the second semiconductor chip being stacked on the first semiconductor chip with the second active surface facing the first active surface; and a conductive interconnection configured to electrically connect the chips. The conductive interconnection includes a first through-electrode that penetrates the second semiconductor chip and electrically connects the second bottom pad to the second top pad; and a second through-electrode that passes through the second top pad without contacting the second top pad, and electrically connects the second bottom pad to the first top pad.

    Abstract translation: 提供了具有贯通电极的半导体器件及其制造方法。 半导体器件可以包括第一半导体芯片，其包括第一有源表面，第一有源表面上设置有第一顶部焊盘; 包括第二有源表面的第二半导体芯片，其上设置有第二顶焊盘，第二非活性表面设置有第二底焊盘，第二半导体芯片堆叠在第一半导体芯片上，第二有源表面面向第一 活性表面 以及被配置为电连接芯片的导电互连。 导电互连包括穿透第二半导体芯片并将第二底部焊盘电连接到第二顶部焊盘的第一贯通电极; 以及第二贯通电极，其穿过所述第二顶部焊盘而不接触所述第二顶部焊盘，并且将所述第二底部焊盘电连接到所述第一顶部焊盘。

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