发明授权
US08811555B2 Clock and data recovery circuitry with auto-speed negotiation and other possible features
有权
时钟和数据恢复电路,具有自动速度协商和其他可能的功能
- 专利标题: Clock and data recovery circuitry with auto-speed negotiation and other possible features
- 专利标题(中): 时钟和数据恢复电路,具有自动速度协商和其他可能的功能
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申请号: US12700433申请日: 2010-02-04
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公开(公告)号: US08811555B2公开(公告)日: 2014-08-19
- 发明人: Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
- 申请人: Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Ropes & Gray LLP
- 主分类号: H04L7/00
- IPC分类号: H04L7/00 ; H03L7/081 ; H04L7/033 ; H03L7/08
摘要:
An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).
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