Invention Grant
US08828819B2 Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode
有权
通过在栅电极的底部产生图案化不均匀性，包括嵌入式应变诱导半导体合金的晶体管中的应变增强
- Patent Title: Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode
- Patent Title (中): 通过在栅电极的底部产生图案化不均匀性，包括嵌入式应变诱导半导体合金的晶体管中的应变增强
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Application No.: US13718346Application Date: 2012-12-18
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Publication No.: US08828819B2Publication Date: 2014-09-09
- Inventor: Stephen Kronholz , Markus Lenski , Vassilios Papageorgiou
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Priority: DE102009023298 20090529
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/336 ; H01L29/49 ; H01L29/423 ; H01L21/28 ; H01L21/8234 ; H01L21/8238 ; H01L29/78
Abstract:
Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.
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