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    Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions
    2.
    发明授权
    Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions 有权
    通过执行湿酸蚀刻工艺同时防止或减少有源区和/或隔离区的损失来形成半导体器件的方法

    公开(公告)号：US08815674B1

    公开(公告)日：2014-08-26

    申请号：US14172135

    申请日：2014-02-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Berthold Reimer ,  Markus Lenski ,  Bastian Haussdoerfer ,  Ardechir Pakfar

    IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/40

    CPC classification number: H01L29/401 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

    Abstract: One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted HF acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.

    Abstract translation: 所公开的一种方法包括在栅极结构附近形成侧壁间隔物，在保护盖层之上形成牺牲层材料，侧壁间隔物和衬底，在牺牲层上形成牺牲保护层，减小牺牲保护层的厚度 使得其上表面位于保护盖层的上表面下方的水平处，执行第一蚀刻工艺以去除牺牲层的一部分，从而露出保护盖层用于进一步处理，执行湿酸 蚀刻工艺，其在蚀刻化学中包括稀释的HF酸以去除保护盖层，并执行至少一个工艺操作以从衬底的表面上方去除至少一个减薄的牺牲保护层或牺牲层。

    Front-end-of-line device structure and method of forming such a front-end-of-line device structure
    4.
    发明授权
    Front-end-of-line device structure and method of forming such a front-end-of-line device structure 有权

    公开(公告)号：US10483154B1

    公开(公告)日：2019-11-19

    申请号：US16015351

    申请日：2018-06-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Elliot John Smith ,  Marcus Wolf ,  Carsten Peters ,  Markus Lenski ,  Loic Gaben

    IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06

    Abstract: In various aspects, the present disclosure relates to device structures and a method of forming such a device structure. In some illustrative embodiments herein, a device is provided, including a semiconductor substrate having a first trench formed therein, and a first trench isolation structure formed in the first trench. The first trench isolation structure includes first and second insulating liners formed adjacent inner surfaces of the first trench, wherein the first insulating liner is in direct contact with inner surfaces of the first trench and the second insulating liner is formed directly on the first insulating liner, and a first insulating filling material which at least partially fills the first trench. In some aspects, a thickness of the first insulating liner is greater than a thickness of the second insulating liner.

    Methods for fabricating integrated circuits with robust gate electrode structure protection
    5.
    发明授权
    Methods for fabricating integrated circuits with robust gate electrode structure protection 有权
    用于制造具有鲁棒栅极电极结构保护的集成电路的方法

    公开(公告)号：US09184260B2

    公开(公告)日：2015-11-10

    申请号：US14080558

    申请日：2013-11-14

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Joanna Wasyluk ,  Dominic Thurmer ,  Ardechir Pakfar ,  Markus Lenski

    IPC: H01L21/425 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/66 ,  H01L29/51 ,  H01L29/165

    CPC classification number: H01L29/6656 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers.

    Abstract translation: 本文提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括形成覆盖半导体衬底的栅电极结构。 第一侧壁间隔件邻近栅电极结构的侧壁形成，并且第一侧壁间隔件包括氮化物。 在形成第一侧壁间隔物之后，将氧化物蚀刻剂施加到半导体衬底的表面。 包括氮化物的第二间隔物材料沉积在半导体衬底和第一侧壁间隔物上，以在将氧化物蚀刻剂施加到半导体衬底的表面之后形成第二间隔层。 用第二间隔物蚀刻剂蚀刻第二间隔层以形成第二侧壁间隔物。

    STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE
    6.
    发明申请
    STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE 有权
    通过在门电极底部形成图案非均匀性来包含嵌入式应变诱导半导体合金的晶体管中的应变增强

    公开(公告)号：US20140339604A1

    公开(公告)日：2014-11-20

    申请号：US14447830

    申请日：2014-07-31

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Stephan Kronholz ,  Markus Lenski ,  Vassilios Papageorgiou

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L27/092

    CPC classification number: H01L29/7848 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51

    Abstract: A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less. A strain-inducing semiconductor alloy is embedded in the semiconductor region laterally adjacent to the bottom portion of the gate electrode structure, and drain and source regions are at least partially positioned in the strain-inducing semiconductor alloy.

    Abstract translation: 半导体器件包括晶体管的栅极电极结构，栅极电极结构位于半导体区域之上并具有包括高k介电材料的栅极绝缘层，位于栅极绝缘层上方的含金属盖材料， 以及位于含金属盖材料上方的栅电极材料。 栅电极结构的底部具有第一长度，并且栅电极结构的上部具有与第一长度不同的第二长度，其中第一长度为约50nm或更小。 应变诱导半导体合金嵌入在与栅电极结构的底部相邻的半导体区域中，并且漏极和源极区域至少部分地位于应变诱导半导体合金中。

    METHODS OF REDUCING MATERIAL LOSS IN ISOLATION STRUCTURES BY INTRODUCING INERT ATOMS INTO OXIDE HARD MASK LAYER USED IN GROWING CHANNEL SEMICONDUCTOR MATERIAL
    9.
    发明申请
    METHODS OF REDUCING MATERIAL LOSS IN ISOLATION STRUCTURES BY INTRODUCING INERT ATOMS INTO OXIDE HARD MASK LAYER USED IN GROWING CHANNEL SEMICONDUCTOR MATERIAL 有权
    降低隔离结构材料损失的方法通过引入入侵物质将氧化物硬掩膜层引入生长通道半导体材料

    公开(公告)号：US20140113419A1

    公开(公告)日：2014-04-24

    申请号：US13654849

    申请日：2012-10-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Thilo Scheiper ,  Jan Hoentschel ,  Markus Lenski ,  Rolf Stephan

    IPC: H01L21/762 ,  H01L21/8238

    CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823807 ,  Y02P80/30

    Abstract: In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process.

    Abstract translation: 在一个示例中，该方法包括在半导体衬底中形成多个隔离结构，其限定第一和第二有源区，其中将分别形成第一和第二晶体管器件，在衬底的表面上形成硬掩模层， 第一和第二有源区，其中所述硬掩模层包括碳，氟，氙或锗离子中的至少一种，执行第一蚀刻工艺以去除所述硬掩模层的一部分并暴露所述第一和第二有源区中的一个的表面 活性区域，在进行第一蚀刻工艺之后，在通过第一蚀刻工艺曝光的有源区的表面上形成沟道半导体材料，并且在形成沟道半导体材料之后，执行第二蚀刻工艺以除去 硬掩模层，其在第一蚀刻工艺期间未被除去。

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