Invention Grant
US08846304B2 Method of forming a pattern in a semiconductor device and method of forming a gate using the same
有权
在半导体器件中形成图案的方法和使用其形成栅极的方法
- Patent Title: Method of forming a pattern in a semiconductor device and method of forming a gate using the same
- Patent Title (中): 在半导体器件中形成图案的方法和使用其形成栅极的方法
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Application No.: US13845851Application Date: 2013-03-18
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Publication No.: US08846304B2Publication Date: 2014-09-30
- Inventor: Choong-Ryul Ryou , Hee-Sung Kang
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Consulting, PLLC
- Priority: KR10-2003-0097427 20031226
- Main IPC: G03F7/26
- IPC: G03F7/26 ; H01L21/311 ; H01L21/28 ; H01L21/3213 ; H01L21/033

Abstract:
A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.
Public/Granted literature
- US20130230979A1 METHOD OF FORMING A PATTERN IN A SEMICONDUCTOR DEVICE AND METHOD OF FORMING A GATE USING THE SAME Public/Granted day:2013-09-05
Information query
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