发明授权
- 专利标题： Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
- 专利标题（中）： 在形成半导体器件期间使用交替间隔物沉积的减径技术及包括其的系统
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申请号： US11484271申请日： 2006-07-10
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公开(公告)号： US08852851B2公开(公告)日： 2014-10-07
- 发明人: Baosuo Zhou , Mirzafer K. Abatchev , Ardavan Niroomand , Paul A. Morgan , Shuang Meng , Joseph N. Greeley , Brian J. Coppa
- 申请人： Baosuo Zhou , Mirzafer K. Abatchev , Ardavan Niroomand , Paul A. Morgan , Shuang Meng , Joseph N. Greeley , Brian J. Coppa
- 申请人地址： US ID Boise
- 专利权人： Micron Technology, Inc.
- 当前专利权人： Micron Technology, Inc.
- 当前专利权人地址： US ID Boise
- 代理机构： Wells St. John P.S.
- 主分类号： H01L21/033
- IPC分类号： H01L21/033 ; H01L21/308
摘要：
A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
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