A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input.