公开(公告)号：US09230690B2

公开(公告)日：2016-01-05

申请号：US13670739

申请日：2012-11-07

Applicant: Apple Inc.

Inventor： Greg M Hess ,  James E Burnette, II

IPC: G11C29/50 ,  G11C8/16

CPC classification number: G11C29/50012 ,  G11C8/16

Abstract: Embodiments of a register file test circuit are disclosed that may allow for determining write performance at low power supply voltages. The register file test circuit may include a decoder, a multiplexer, a frequency divider, and a control circuit. The decoder may be operable to select a register cell within a register file, and the control circuit may be operable to controllably activate the read and write paths through the selected register cell, allowing data read to be inverted and re-written back into the selected register cell.

Abstract translation: 公开了寄存器文件测试电路的实施例，其可以允许在低电源电压下确定写入性能。 寄存器文件测试电路可以包括解码器，复用器，分频器和控制电路。 解码器可以用于选择寄存器文件中的寄存器单元，并且控制电路可操作以可控制地激活通过所选择的寄存器单元的读取和写入路径，从而允许将数据读取反向并重写回所选择的寄存器单元 寄存器单元格。

公开(公告)号：US09001593B2

公开(公告)日：2015-04-07

申请号：US13725180

申请日：2012-12-21

Applicant: Apple Inc.

Inventor： Hitesh Gupta ,  Greg M Hess ,  Aravind Kandala

IPC: G11C16/10 ,  G11C8/08

CPC classification number: G11C8/08 ,  G11C8/10

Abstract: A memory array includes a number of word lines, with each word line coupled to a word line driver for memory write operations and a word line driver for memory read operations. A decode stage includes write logic for each word line and read logic for each word line. A word line driver stage includes a write word line driver and a read word line driver. The write logic for at least one world line is configured to enable the write word line driver for a memory write operation of the word line while prohibiting the read word line logic from enabling the read word line driver for a memory read operation of the word line.

Abstract translation: 存储器阵列包括多个字线，每个字线耦合到用于存储器写入操作的字线驱动器和用于存储器读取操作的字线驱动器。 解码级包括每个字线的写逻辑和每个字线的读逻辑。 字线驱动器级包括写字线驱动器和读字线驱动器。 用于至少一个世界线的写入逻辑被配置为使得写入字线驱动器能够进行字线的存储器写入操作，同时禁止读取字线逻辑使读取字线驱动器用于字线的存储器读取操作 。

公开(公告)号：US08860464B2

公开(公告)日：2014-10-14

申请号：US13725784

申请日：2012-12-21

Applicant: Apple Inc.

Inventor： Hitesh K Gupta ,  Greg M Hess ,  Naveen Javarappa

IPC: H03K3/037 ,  H03K19/00 ,  G11C7/00

CPC classification number: G11C7/00 ,  G11C29/1201 ,  G11C29/32 ,  G11C29/48 ,  H03K3/356121 ,  H03K3/356173 ,  H03K19/00

Abstract: A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input.

Abstract translation: 零保持器电路包括连接到源，输出和动态输入的动态输入PFET。 电路还包括连接到输出的时钟输入NFET，下拉节点和时钟输入。 电路还包括连接到下拉节点的动态输入NFET，参考电压和动态输入。 电路还包括反馈PFET和在源极和输出端之间串联连接的时钟输入PFET。 反馈PFET接收反馈信号，时钟输入PFET接收时钟输入。 电路还包括连接到输出端和节点的反馈NFET。 反馈NFET被配置为基于反馈信号将输出耦合到节点。 电路还包括被配置为基于输出和旁路输入提供反馈信号的或非门。

公开(公告)号：US09207705B2

公开(公告)日：2015-12-08

申请号：US13670779

申请日：2012-11-07

Applicant: Apple Inc.

Inventor： Greg M Hess ,  James E Burnette, II

IPC: G01R31/28 ,  G06F1/04 ,  G01R31/3185 ,  G01R31/317 ,  H03M1/20 ,  H03M1/08

CPC classification number: G06F1/04 ,  G01R31/31709 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/31858 ,  G01R31/318594 ,  G11B20/10398 ,  H03M1/0836 ,  H03M1/205 ,  H04L1/205

Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.

Abstract translation: 公开了可以允许在时钟分配网络中检测周期和相位抖动的抖动检测电路的实施例。 抖动检测电路可以包括相位选择器，数据发生器，延迟链，逻辑电路和时钟存储元件。 相位选择器可以用于选择要用于发射时钟的时钟相位，并且数据发生器可以用于响应于发射时钟产生数据信号。 延迟链可以产生取决于数据信号的多个输出，并且时钟控制的存储元件可以用于从延迟链捕获多个输出，其可以通过逻辑电路与预期数据进行比较。

公开(公告)号：US08988957B2

公开(公告)日：2015-03-24

申请号：US13670813

申请日：2012-11-07

Applicant: Apple Inc.

Inventor： Greg M Hess ,  James E Burnette, II

IPC: G11C29/00 ,  H01L21/66 ,  G11C29/02

CPC classification number: H01L22/12 ,  G11C29/026 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sense amplifier test circuit that may allow for detecting soft failures may include a voltage generator circuit, a sense amplifier, and a detection circuit. The voltage generator may be operable to controllably supply different differential voltages to the sense amplifier, and the detection circuit may be operable to detect an analog voltage on the output of the sense amplifier.

Abstract translation: 可以允许检测软故障的感测放大器测试电路可以包括电压发生器电路，读出放大器和检测电路。 电压发生器可操作以可控制地向感测放大器提供不同的差分电压，并且检测电路可以用于检测读出放大器的输出上的模拟电压。

公开(公告)号：US20140129868A1

公开(公告)日：2014-05-08

申请号：US13670779

申请日：2012-11-07

Applicant: APPLE INC.

Inventor： Greg M Hess ,  James E Burnette, II

IPC: G06F1/08

CPC classification number: G06F1/04 ,  G01R31/31709 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/31858 ,  G01R31/318594 ,  G11B20/10398 ,  H03M1/0836 ,  H03M1/205 ,  H04L1/205

Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.

Abstract translation: 公开了可以允许在时钟分配网络中检测周期和相位抖动的抖动检测电路的实施例。 抖动检测电路可以包括相位选择器，数据发生器，延迟链，逻辑电路和时钟存储元件。 相位选择器可以用于选择要用于发射时钟的时钟相位，并且数据发生器可以用于响应于发射时钟产生数据信号。 延迟链可以产生取决于数据信号的多个输出，并且时钟控制的存储元件可以用于从延迟链捕获多个输出，其可以通过逻辑电路与预期数据进行比较。