A memory apparatus is provided. The memory apparatus includes a first memory chip, a second memory chip and a control unit configured to manage a first mapping table for the first memory chip and a second mapping table for the second memory chip. If a first physical address of the second memory chip is allocated to a first logical address of the first memory chip, the control unit is configured to update a second logical address of the second memory chip to correspond to the first physical address of the second memory chip in the second mapping table and update the first logical address of the first memory chip to correspond to the second logical address of the second memory chip in the first mapping table.