Invention Grant
US08932911B2 Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
有权
用于制造在金属触点和互连之间具有覆盖层的集成电路的集成电路和方法
- Patent Title: Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
- Patent Title (中): 用于制造在金属触点和互连之间具有覆盖层的集成电路的集成电路和方法
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Application No.: US13778558Application Date: 2013-02-27
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Publication No.: US08932911B2Publication Date: 2015-01-13
- Inventor: Torsten Huisinga , Carsten Peters , Andreas Ott , Axel Preusse
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/82 ; H01L21/311 ; H01L21/44 ; H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L21/02 ; H01L21/768
Abstract:
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.
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