Invention Grant
US08935489B2 Adaptively time-multiplexing memory references from multiple processor cores
有权
适应时间多路复用多个处理器内核的内存引用
- Patent Title: Adaptively time-multiplexing memory references from multiple processor cores
- Patent Title (中): 适应时间多路复用多个处理器内核的内存引用
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Application No.: US13500067Application Date: 2010-11-10
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Publication No.: US08935489B2Publication Date: 2015-01-13
- Inventor: Steven C. Woo , Trung A. Diep , Michael T. Ching
- Applicant: Steven C. Woo , Trung A. Diep , Michael T. Ching
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: The Neudeck Law Firm, LLC
- International Application: PCT/US2010/056195 WO 20101110
- International Announcement: WO2011/090537 WO 20110728
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/16 ; G06F9/52

Abstract:
The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.
Public/Granted literature
- US20120278583A1 ADAPTIVELY TIME-MULTIPLEXING MEMORY REFERENCES FROM MULTIPLE PROCESSOR CORES Public/Granted day:2012-11-01
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