公开(公告)号：US08935489B2

公开(公告)日：2015-01-13

申请号：US13500067

申请日：2010-11-10

申请人： Steven C. Woo ,  Trung A. Diep ,  Michael T. Ching

发明人： Steven C. Woo ,  Trung A. Diep ,  Michael T. Ching

IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F9/52

CPC分类号： G06F13/1652 ,  G06F9/5016 ,  G06F9/52

摘要： The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.

摘要翻译： 所公开的实施例涉及用于处理从多个处理器核心接收的存储器参考的系统。 在操作期间，系统监视存储器引用以确定来自不同处理器核的存储器引用是否因存储器引用被存储器系统处理而彼此干扰。 如果来自不同处理器核心的存储器引用彼此干扰，则系统对处理器内核之间的存储器引用进行时间复用，从而在存储器引用之前由存储器系统处理来自给定处理器内核的连续存储器引用块 处理其他处理器内核。

公开(公告)号：US20120278583A1

公开(公告)日：2012-11-01

申请号：US13500067

申请日：2010-11-10

申请人： Steven C. Woo ,  Trung A. Diep ,  Michael T. Ching

发明人： Steven C. Woo ,  Trung A. Diep ,  Michael T. Ching

IPC分类号： G06F12/00

CPC分类号： G06F13/1652 ,  G06F9/5016 ,  G06F9/52

摘要： The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.

摘要翻译： 所公开的实施例涉及用于处理从多个处理器核心接收的存储器参考的系统。 在操作期间，系统监视存储器引用以确定来自不同处理器核的存储器引用是否因存储器引用被存储器系统处理而彼此干扰。 如果来自不同处理器核心的存储器引用彼此干扰，则系统对处理器内核之间的存储器引用进行时间复用，从而在存储器引用之前由存储器系统处理来自给定处理器内核的连续存储器引用块 处理其他处理器内核。

公开(公告)号：US07194056B2

公开(公告)日：2007-03-20

申请号：US09891578

申请日：2001-06-25

申请人： Jun Kim ,  Michael T. Ching

发明人： Jun Kim ,  Michael T. Ching

IPC分类号： H04L7/00

CPC分类号： G11C7/1066 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H04L7/0012 ,  H04L7/0045

摘要： Disclosed herein are circuits in which a plurality of clock signals are generated by corresponding clock generators from one or more common clock references. The clock generators accept control values that specify the phases of the individual clocks. The actual phase of each clock signal potentially varies during operation, and the phases of the various clock signal are generally independent of each other. To detect or measure phase relationships, the disclosed circuits evaluate or compare the control values using arithmetic logic.

摘要翻译： 这里公开了其中通过来自一个或多个公共时钟参考的相应时钟发生器产生多个时钟信号的电路。 时钟发生器接受指定各个时钟的相位的控制值。 每个时钟信号的实际相位可能在操作期间变化，并且各种时钟信号的相位通常彼此独立。 为了检测或测量相位关系，所公开的电路使用算术逻辑来评估或比较控制值。