Invention Grant
- Patent Title: Method and apparatus for optimizing power and latency on a link
- Patent Title (中): 用于优化链路上的功率和延迟的方法和装置
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Application No.: US13631934Application Date: 2012-09-29
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Publication No.: US08935578B2Publication Date: 2015-01-13
- Inventor: James W. Alexander , Buck W. Gremel , Pinkesh J. Shah , Malay Trivedi , Mohan K. Nair
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Carrie A. Boone, P.C.
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.
Public/Granted literature
- US20140095944A1 METHOD AND APPARATUS FOR OPTIMIZING POWER AND LATENCY ON A LINK Public/Granted day:2014-04-03
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