公开(公告)号：US09183144B2

公开(公告)日：2015-11-10

申请号：US13715613

申请日：2012-12-14

Applicant: Intel Corporation

Inventor： Ren Wang ,  Ahmad Samih ,  Eric Delano ,  Pinkesh J. Shah ,  Zeshan A. Chishti ,  Christian Maciocco ,  Tsung-Yuan Charlie Tai

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F1/32 ,  G06F1/3215 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0811 ,  G06F2212/1028 ,  Y02D10/13

Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

公开(公告)号：US09176875B2

公开(公告)日：2015-11-03

申请号：US13785228

申请日：2013-03-05

Applicant: Intel Corporation

Inventor： Ren Wang ,  Ahmad Samih ,  Eric Delano ,  Pinkesh J. Shah ,  Zeshan A. Chishti ,  Christian Maciocco ,  Tsung-Yuan Charlie Tai

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F1/32 ,  G06F1/3215 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0811 ,  G06F2212/1028 ,  Y02D10/13

Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个瓦片，每个瓦片包括核心和瓦片高速缓存层级。 该瓦片高速缓存层级包括第一级高速缓存，中级缓存（MLC）和最后级高速缓存（LLC），并且这些高速缓存中的每一个对于该瓦片是私有的。 耦合到瓦片的控制器包括高速缓存功率控制逻辑，用于至少部分地基于该信息来接收关于瓦片的核心和瓦片高速缓存层级的利用信息，并且使瓦片的LLC独立地进行电源门控。 描述和要求保护其他实施例。

公开(公告)号：US08935578B2

公开(公告)日：2015-01-13

申请号：US13631934

申请日：2012-09-29

Applicant: Intel Corporation

Inventor： James W. Alexander ,  Buck W. Gremel ,  Pinkesh J. Shah ,  Malay Trivedi ,  Mohan K. Nair

IPC: G06F11/00

CPC classification number: G06F1/3253 ,  Y02D10/151

Abstract: An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.

Abstract translation: 公开了一种用于优化在基于处理器的系统内操作的链路的等待时间和功率的装置和方法。 该装置和方法包括内置于不依赖于队列深度阈值的队列中的等待时间计。 该装置和方法还包括反馈逻辑，其优化围绕增加的延迟目标的功率降低以对由链路的物理属性施加的缓慢的重新供应行为作出反应。