Invention Grant
- Patent Title: Device isolation in finFET CMOS
- Patent Title (中): finFET CMOS器件隔离
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Application No.: US13906852Application Date: 2013-05-31
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Publication No.: US08963259B2Publication Date: 2015-02-24
- Inventor: Ajey P. Jacob , Murat K. Akarvardar , Steven J. Bentley , Toshiharu Nagumo , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz
- Applicant: GlobalFoundries Inc.
- Applicant Address: KY Grand Cayman US NY Armonk JP Kanagawa
- Assignee: GlobalFoundries Inc.,International Business Machines Corporation,Renesas Electronics Corporation
- Current Assignee: GlobalFoundries Inc.,International Business Machines Corporation,Renesas Electronics Corporation
- Current Assignee Address: KY Grand Cayman US NY Armonk JP Kanagawa
- Agency: Williams Morgan, P.C.
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119 ; H01L21/761 ; H01L29/06 ; H01L21/762

Abstract:
Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.
Public/Granted literature
- US20140353801A1 DEVICE ISOLATION IN FINFET CMOS Public/Granted day:2014-12-04
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