Invention Grant
- Patent Title: Methods for manufacturing metal gates
- Patent Title (中): 制造金属门的方法
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Application No.: US13865285Application Date: 2013-04-18
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Publication No.: US08987080B2Publication Date: 2015-03-24
- Inventor: Xinliang Lu , Seshadri Ganguli , Atif Noori , Maitreyee Mahajani , Shih Chung Chen , Yu Lei , Xinyu Fu , Wei Tang , Srinivas Gandikota
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Servilla Whitney LLC
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/8234 ; H01L29/66 ; H01L21/8238 ; H01L21/28 ; H01L21/322 ; H01L29/49 ; H01L29/78

Abstract:
Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first.
Public/Granted literature
- US20130295759A1 Methods For Manufacturing Metal Gates Public/Granted day:2013-11-07
Information query
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