Invention Grant
- Patent Title: Methods and systems to stress-program an integrated circuit
- Patent Title (中): 压力编程集成电路的方法和系统
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Application No.: US13768411Application Date: 2013-02-15
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Publication No.: US09018975B2Publication Date: 2015-04-28
- Inventor: Nicholas P. Cowley , Ramnarayanan Muthukaruppan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Garrett IP, LLC
- Main IPC: H03K19/173
- IPC: H03K19/173 ; G11C17/18

Abstract:
Methods and systems to stress-program a first integrated circuit (IC) block to output a pre-determined value upon activation/reset, such as to support time-zero compensation/trimming. To program, the first block is configured with first-block program parameters to cause the first block to output a pre-determined value. The first block is stressed while configured with the first-block program parameters, to cause the first block to output the pre-determined value without the first-block program parameters. The first block may include a latch designed as a fully balance circuit and may be asymmetrically stressed to alter a characteristic of one path relative to another. The pre-determined value may be selected to compensate for process corner variations and/or other random variations.
Public/Granted literature
- US20140232430A1 METHODS AND SYSTEMS TO STRESS-PROGRAM AN INTEGRATED CIRCUIT Public/Granted day:2014-08-21
Information query
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