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公开(公告)号：US11619960B2
公开(公告)日：2023-04-04
申请号：US17354932
申请日：2021-06-22
Applicant: Intel Corporation
Inventor： Tarun Mahajan , Ramnarayanan Muthukaruppan , Rajesh Sidana , Srinath B. Pai
Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a control circuitry to generate error information based on a value of the feedback voltage generated from an output voltage, generate output information to control a power switching unit based on the error information provided to a forward path in the control circuitry, and adjust a gain of the forward path based on a gain factor computed based at least in part on a first value of the output information in order to cause the output information to have a second value. The control circuitry also computes a value of correction information when the output voltage is within a target value range, and adjusts the control information, based on the correction information, when the output voltage is outside the target value range.
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公开(公告)号：US10990146B2
公开(公告)日：2021-04-27
申请号：US16359810
申请日：2019-03-20
Applicant: Intel Corporation
Inventor： Ramnarayanan Muthukaruppan , Pradipta Patra , Gaurav Goel , Uday Bhaskar Kadali
Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
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公开(公告)号：US20170322581A1
公开(公告)日：2017-11-09
申请号：US15595781
申请日：2017-05-15
Applicant: Intel Corporation
Inventor： Rupak Ghayal , Pradipta Patra , Ramnarayanan Muthukaruppan , Raghu Nandan Chepuri
IPC: G05F3/02
CPC classification number: G05F3/02
Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
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公开(公告)号：US20160164500A1
公开(公告)日：2016-06-09
申请号：US14560073
申请日：2014-12-04
Applicant: Intel Corporation
Inventor： Santosh Nene , Tarun Mahajan , Venkataraman Srinivasan , Ramnarayanan Muthukaruppan
CPC classification number: H03K5/1565 , G01R19/25 , G01R19/2506 , H02M1/088 , H02M3/158 , H02M2001/0009 , H02M2001/0022 , H03K3/017
Abstract: Some embodiments include apparatus and methods having a node to provide a signal, and a control unit arranged to control a value of an output voltage at an output node on an output path based on a duty cycle of the signal and a value of an input voltage. The control unit can also be arranged to cause a change in a resistance on the output path in order to determine a value of a current on the output path based at least on the change in the resistance.
Abstract translation: 一些实施例包括具有提供信号的节点的装置和方法，以及控制单元，其被配置为基于信号的占空比和输入电压的值来控制输出路径上的输出节点处的输出电压的值 。 控制单元还可以被布置成使得输出路径上的电阻发生变化，以便至少基于电阻的变化确定输出路径上的电流值。
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公开(公告)号：US10345881B2
公开(公告)日：2019-07-09
申请号：US15653764
申请日：2017-07-19
Applicant: Intel Corporation
Inventor： Ramnarayanan Muthukaruppan , Harish K. Krishnamurthy , Mohit Verma , Pradipta Patra , Uday Bhaskar Kadali
IPC: G06F9/00 , G06F1/32 , G06F1/3234 , G06F1/3296 , G06F1/324
Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
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Patent Agency Ranking
公开(公告)号：US10268249B2
公开(公告)日：2019-04-23
申请号：US15025871
申请日：2013-12-18
Applicant: Intel Corporation
Inventor： Ramnarayanan Muthukaruppan , Pradipta Patra , Gaurav Goel , Uday Bhaskar Kadali
Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
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公开(公告)号：US09651978B2
公开(公告)日：2017-05-16
申请号：US14689600
申请日：2015-04-17
Applicant: Intel Corporation
Inventor： Rupak Ghayal , Pradipta Patra , Ramnarayanan Muthukaruppan , Raghu Nandan Chepuri
CPC classification number: G05F3/02
Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
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公开(公告)号：US20160306374A1
公开(公告)日：2016-10-20
申请号：US14689600
申请日：2015-04-17
Applicant: Intel Corporation
Inventor： Rupak Ghayal , Pradipta Patra , Ramnarayanan Muthukaruppan , Raghu Nandan Chepuri
IPC: G05F3/02 , H03K17/687
CPC classification number: G05F3/02
Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
Abstract translation: 描述了用于电力管理的装置和方法。 该装置可以包括包括多个电流源的电源门。 电源门可以耦合到负载。 该装置还可以包括耦合到功率门的电压控制电路，以确定并选择多个电流源中的一个或多个电流源来提供给负载。 该装置还可以包括耦合到电压控制电路的电流控制电路，以控制一个或多个电流源的各个电流源以输出恒定电流。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US09018975B2
公开(公告)日：2015-04-28
申请号：US13768411
申请日：2013-02-15
Applicant: Intel Corporation
Inventor： Nicholas P. Cowley , Ramnarayanan Muthukaruppan
IPC: H03K19/173 , G11C17/18
CPC classification number: H03K19/173 , G11C17/18
Abstract: Methods and systems to stress-program a first integrated circuit (IC) block to output a pre-determined value upon activation/reset, such as to support time-zero compensation/trimming. To program, the first block is configured with first-block program parameters to cause the first block to output a pre-determined value. The first block is stressed while configured with the first-block program parameters, to cause the first block to output the pre-determined value without the first-block program parameters. The first block may include a latch designed as a fully balance circuit and may be asymmetrically stressed to alter a characteristic of one path relative to another. The pre-determined value may be selected to compensate for process corner variations and/or other random variations.
Abstract translation: 压缩程序化第一集成电路（IC）块以在激活/复位时输出预定值的方法和系统，例如支持时间零补偿/修整。 为了编程，第一块被配置有第一块程序参数，以使第一块输出预定值。 第一个程序段被配置了第一个程序段的第一个程序参数，使第一个程序段输出预定义的值，而没有第一个程序参数。 第一块可以包括被设计为完全平衡电路的闩锁，并且可以是不对称应力以改变相对于另一路径的一个路径的特性。 可以选择预定值以补偿过程角变化和/或其他随机变化。
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公开(公告)号：US20230412712A1
公开(公告)日：2023-12-21
申请号：US18459688
申请日：2023-09-01
Applicant: Intel Corporation
Inventor： Nayan Suthar , Mark Debbage , Ramnarayanan Muthukaruppan
CPC classification number: H04L69/22 , H04L2212/00 , H04L45/74
Abstract: Described herein are optimized packet headers for Ethernet IP networks and related methods and devices. An example packet header includes a field comprising a source identifier (SID), the SID comprising a shortened representation of a complete Internet Protocol (IP) address of a source network device, a field comprising a destination identifier (DID), the DID comprising a shortened representation of a complete IP address of a destination network device, and a field having a total number of bits that is less than 8 and comprising a shortened representation of a type of encapsulation protocol for the packet. The packet header excludes fields comprising the complete IP address and a media access controller (MAC) address of the source network device, fields comprising the complete IP address and the MAC address of the destination network device, a field comprising a header checksum, and a field comprising a total size of the packet.
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