Invention Grant
- Patent Title: Termination circuit, semiconductor device, and test system
- Patent Title (中): 终端电路，半导体器件和测试系统
-
Application No.: US13961112Application Date: 2013-08-07
-
Publication No.: US09069043B2Publication Date: 2015-06-30
- Inventor: Toshihide Suzuki , Yoichi Kawano
- Applicant: FUJITSU LIMITED
- Applicant Address: JP Kawasaki
- Assignee: FUJITSU LIMITED
- Current Assignee: FUJITSU LIMITED
- Current Assignee Address: JP Kawasaki
- Agency: Kratz, Quintos & Hanson, LLP
- Main IPC: H03K17/16
- IPC: H03K17/16 ; H03K19/003 ; G01R31/3183 ; H04L25/02 ; H03H11/30 ; H03F1/56 ; G01R31/28 ; H04B1/04
Abstract:
A termination circuit includes a pMOS transistor configured to have a source connected with a signal terminal outputting or inputting a transmission signal, a drain connected with a grounding line, and a gate receiving a control signal, the pMOS transistor being turned on when enabling a characteristic impedance matching function and being turned off when disabling the matching function; and an inductor and a capacitor configured to be connected with the signal terminal for matching characteristic impedance.
Public/Granted literature
- US20130326300A1 TERMINATION CIRCUIT, SEMICONDUCTOR DEVICE, AND TEST SYSTEM Public/Granted day:2013-12-05
Information query
