发明授权
- 专利标题: Dynamic error handling using parity and redundant rows
- 专利标题(中): 使用奇偶校验和冗余行的动态错误处理
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申请号: US13327845申请日: 2011-12-16
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公开(公告)号: US09075741B2公开(公告)日: 2015-07-07
- 发明人: Altug Koker , Shailesh Shah , Aditya Navale , Murali Ramadoss , Satish K. Damaraju
- 申请人: Altug Koker , Shailesh Shah , Aditya Navale , Murali Ramadoss , Satish K. Damaraju
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理商 Thomas R. Lane
- 主分类号: G06F11/00
- IPC分类号: G06F11/00 ; G06F11/10 ; H03M13/09 ; H04L1/00 ; H03M13/11
摘要:
Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.
公开/授权文献
- US20130159820A1 DYNAMIC ERROR HANDLING USING PARITY AND REDUNDANT ROWS 公开/授权日:2013-06-20
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