公开(公告)号：US10424043B1

公开(公告)日：2019-09-24

申请号：US16025718

申请日：2018-07-02

申请人： Joseph Koston ,  Ankur Shah ,  Murali Ramadoss ,  Jeffery Boles ,  Balaji Vembu

发明人： Joseph Koston ,  Ankur Shah ,  Murali Ramadoss ,  Jeffery Boles ,  Balaji Vembu

IPC分类号： G06T1/20 ,  G06F21/74 ,  G06T15/00 ,  G06F9/50 ,  G06T1/60 ,  G09G5/36

摘要： Graphics processing systems and methods are described. A graphics processing apparatus may comprise one or more graphics processing cores, a shared buffer accessible to a user mode driver (UMD) associated with an application in an unprivileged domain, the UMD to write one or more commands to the shared buffer, and a controller parse a workload in the shared buffer to identify one or more commands in the workload, the workload added by the application executing in the unprivileged domain, associate a trigger with a command in the workload, transfer the workload to one or more components of the graphics processing apparatus for execution, and upon execution of the command associated with the trigger, sample the shared buffer to identify a new workload added to the shared buffer. The one or more components of the graphics processing apparatus automatically execute the new workload added to the shared buffer.

公开(公告)号：US20190227801A1

公开(公告)日：2019-07-25

申请号：US15879416

申请日：2018-01-24

申请人： RAJESH SANKARAN ,  ANKUR SHAH ,  BRYAN WHITE ,  HEMA NALLURI ,  DAVID PUFFER ,  MURALI RAMADOSS ,  ALTUG KOKER ,  ADITYA NAVALE ,  BALAJI VEMBU

发明人： RAJESH SANKARAN ,  ANKUR SHAH ,  BRYAN WHITE ,  HEMA NALLURI ,  DAVID PUFFER ,  MURALI RAMADOSS ,  ALTUG KOKER ,  ADITYA NAVALE ,  BALAJI VEMBU

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F12/1009 ,  G06T1/20

摘要： An apparatus and method for scalable interrupt reporting. For example, one embodiment of an apparatus comprises: a host processor to execute one or more processes having a corresponding one or more process contexts associated therewith; and a graphics processing engine to, upon initiating execution of a first process, determine a current process context associated with the first process including a first pointer to a first system memory region to store an interrupt status, a second pointer to a second system memory region to store interrupt enable and/or interrupt mask data for one or more interrupt events, and address/data values associated with a message signaled interrupt (MSI); the graphics processing engine, in response to an interrupt event, to evaluate the interrupt enable data from the second system memory region to determine whether the interrupt event is enabled, to report the interrupt event, if enabled, by writing a specified value to the first system memory region identified by the first pointer, and to generate a first MSI corresponding to the interrupt event by writing the MSI address/data values to an output accessible by the host processor.

公开(公告)号：US09659342B2

公开(公告)日：2017-05-23

申请号：US13931915

申请日：2013-06-29

申请人： Hema Chand Nalluri ,  Aditya Navale ,  Murali Ramadoss ,  Jeffery S. Boles

发明人： Hema Chand Nalluri ,  Aditya Navale ,  Murali Ramadoss ,  Jeffery S. Boles

IPC分类号： G06F9/48 ,  G06T1/60 ,  G06T1/20

CPC分类号： G06T1/60 ,  G06F9/48 ,  G06F9/485 ,  G06T1/20

摘要： Mid-command buffer preemption is described for graphics workloads in a graphics processing environment. In one example, instructions of a first context are executed at a graphics processor, the first context has a sequence of instructions in an addressable buffer and at least one of the instructions is a preemption instruction. Upon executing the preemption instruction, execution of the first context is stopped before the sequence of instructions is completed. An address is stored for an instruction with which the first context will be resumed. The second context is executed, and upon completion of the execution of the second context, the execution of the first context is resumed at the stored address.

公开(公告)号：US20140208047A1

公开(公告)日：2014-07-24

申请号：US13977295

申请日：2011-12-28

申请人： Balaji Vembu ,  Murali Ramadoss

发明人： Balaji Vembu ,  Murali Ramadoss

IPC分类号： G06F3/06

CPC分类号： G06F3/0638 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/0292 ,  G06F2212/205 ,  G06T1/60 ,  G11C14/0045 ,  Y02D10/13

摘要： A method, device, and system to distribute code and data stores between volatile and non-volatile memory are described. In one embodiment, the method includes storing one or more static code segments of a software application in a phase change memory with switch (PCMS) device, storing one or more static data segments of the software application in the PCMS device, and storing one or more volatile data segments of the software application in a volatile memory device. The method then allocates an address mapping table with at least a first address pointer to point to each of the one or more static code segments, at least a second address pointer to point to each of the one or more static data segments, and at least a third address pointer to point to each of the one or more volatile data segments.

摘要翻译： 描述了在易失性和非易失性存储器之间分发代码和数据存储的方法，设备和系统。 在一个实施例中，该方法包括将具有交换机（PCMS）设备的软件应用的一个或多个静态代码段存储在相变存储器中，将该软件应用的一个或多个静态数据段存储在PCMS设备中，并存储一个或多个 在易失性存储器件中软件应用的更易变的数据段。 该方法然后将至少一个第一地址指针的地址映射表分配给一个或多个静态代码段中的每一个，至少第二地址指针指向一个或多个静态数据段中的每一个，并且至少 指向一个或多个易失性数据段中的每一个的第三地址指针。

公开(公告)号：US20140204101A1

公开(公告)日：2014-07-24

申请号：US13997206

申请日：2011-11-30

申请人： Murali Ramadoss ,  Eric C. Samson

发明人： Murali Ramadoss ,  Eric C. Samson

IPC分类号： G06T1/20

CPC分类号： G09G5/18 ,  G06F1/324 ,  G06F1/3265 ,  G06F3/14 ,  G06T1/20 ,  G06T1/60 ,  G09G2330/021 ,  G09G2340/0435 ,  Y02D10/126 ,  Y02D10/153 ,  Y02D50/20

摘要： Examples are disclosed for adjusting a performance state of a graphics subsystem and/or a processor based on a comparison of an average frame rate to a target frame rate and also based on whether the graphics subsystem is in a burst mode or sustained mode of operation.

摘要翻译： 公开了用于基于平均帧速率与目标帧速率的比较以及基于图形子系统是否处于突发模式或持续操作模式来调整图形子系统和/或处理器的性能状态的示例。

公开(公告)号：US20140104287A1

公开(公告)日：2014-04-17

申请号：US13649798

申请日：2012-10-11

申请人： Hema C. Nalluri ,  Aditya Navale ,  Murali Ramadoss

发明人： Hema C. Nalluri ,  Aditya Navale ,  Murali Ramadoss

IPC分类号： G06T15/00

CPC分类号： G06F21/74 ,  G06F21/84 ,  G06T15/005

摘要： Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged. A graphics processing unit (GPU) can receive the privilege-designated batch buffers from the KMD, and is configured to disallow execution of any privileged command from a non-privileged batch buffer, while any privileged commands from privileged batch buffers are unrestricted by the GPU

摘要翻译： 公开了用于以安全方式处理图形系统的渲染引擎工作负载的技术，其中将工作负载的至少一些安全处理从基于软件的安全解析卸载到基于硬件的安全解析。 在一些实施例中，来自给定应用的命令由用户模式驱动程序（UMD）接收，用户模式驱动程序（UMD）被配置为生成描绘为特权和/或非特权命令部分的命令缓冲器。 所描绘的命令缓冲区然后可以被UMD传递给内核模式驱动程序（KMD），该驱动程序被配置为仅解析和验证特权缓冲区段，而是发出所有其他批处理缓冲区，其特权指示符设置为非特权。 图形处理单元（GPU）可以从KMD接收特权指定的批量缓冲区，并且配置为不允许从非特权批处理缓冲区执行任何特权命令，而来自特权批处理缓冲区的任何特权命令都不受GPU限制

公开(公告)号：US20120223954A1

公开(公告)日：2012-09-06

申请号：US13469395

申请日：2012-05-11

申请人： Eric Samson ,  Murali Ramadoss

发明人： Eric Samson ,  Murali Ramadoss

IPC分类号： G06F13/14

CPC分类号： G06T1/00 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/50 ,  G06F11/3409 ,  G06F11/348 ,  G06T1/20 ,  G09G5/001 ,  G09G5/363 ,  G09G2330/021 ,  Y02D10/126 ,  Y02D10/22 ,  Y02D10/34

摘要： In accordance with some embodiments, a graphics process frame generation frame rate may be monitored in combination with a utilization or work load metric for the graphics process in order to allocate performance resources to the graphics process and in some cases, between the graphics process and a central processing unit.

摘要翻译： 根据一些实施例，可以结合图形处理的利用率或工作负载量度来监视图形处理帧生成帧速率，以便为图形处理分配性能资源，并且在一些情况下，在图形处理和 中央处理器。

公开(公告)号：US09563466B2

公开(公告)日：2017-02-07

申请号：US14072622

申请日：2013-11-05

申请人： Hema Chand Nalluri ,  Jeffery S. Boles ,  Murali Ramadoss ,  Aditya Navale ,  Lalit K. Saptarshi

发明人： Hema Chand Nalluri ,  Jeffery S. Boles ,  Murali Ramadoss ,  Aditya Navale ,  Lalit K. Saptarshi

IPC分类号： G06F9/46 ,  G06T1/20

CPC分类号： G06F9/461 ,  G06T1/20

摘要： A method and apparatus for supporting programmable software context state execution during hardware context restore flow is described. In one example, a context ID is assigned to graphics applications including a unique context memory buffer, a unique indirect context pointer and a corresponding size to each context ID, an indirect context offset, and an indirect context buffer address range. When execution of the first context workload is indirected, the state of the first context workload is saved to the assigned context memory buffer. The indirect context pointer, the indirect context offset and a size of the indirect context buffer address range are saved to registers that are independent of the saved context state. The context is restored by accessing the saved indirect context pointer, the indirect context offset and the buffer size.

摘要翻译： 描述了用于在硬件上下文恢复流程期间支持可编程软件上下文状态执行的方法和装置。 在一个示例中，上下文ID被分配给包括唯一上下文存储器缓冲器，唯一间接上下文指针和对每个上下文ID，间接上下文偏移以及间接上下文缓冲器地址范围的对应大小的图形应用。 当第一上下文工作负载的执行被间接时，第一上下文工作负载的状态被保存到所分配的上下文存储器缓冲器中。 间接上下文指针，间接上下文偏移量和间接上下文缓冲区地址范围的大小保存到独立于保存的上下文状态的寄存器中。 通过访问保存的间接上下文指针，间接上下文偏移量和缓冲区大小来恢复上下文。

公开(公告)号：US09317892B2

公开(公告)日：2016-04-19

申请号：US13977261

申请日：2011-12-28

申请人： Bryan E. Veal ,  Travis T. Schluessler ,  Murali Ramadoss ,  Balaji Vembu

发明人： Bryan E. Veal ,  Travis T. Schluessler ,  Murali Ramadoss ,  Balaji Vembu

IPC分类号： G09G5/39 ,  G06T1/60 ,  G11C16/34

CPC分类号： G06T1/60 ,  G11C16/349

摘要： Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.

摘要翻译： 描述了在具有某些类型的非易失性存储器的图形子系统中增加易失性存储器的方法和装置。 在一个实施例中，包括将一个或多个静态或近静态图形资源存储在非易失性随机存取存储器（NVRAM）中。 NVRAM可直接由图形处理器使用，至少使用内存存储和加载命令。 该方法还包括执行图形应用的图形处理器。 图形处理器使用存储器加载命令来发送对应于存储在NVRAM中的至少一个静态或近静态图形资源的地址的请求。 该方法还包括响应于存储器加载命令将所请求的图形资源从NVRAM直接加载到图形处理器的高速缓存中。

公开(公告)号：US09304813B2

公开(公告)日：2016-04-05

申请号：US13552122

申请日：2012-07-18

申请人： Balaji Vembu ,  Aditya Navale ,  Murali Ramadoss ,  David I. Standring ,  Kritika Bala

发明人： Balaji Vembu ,  Aditya Navale ,  Murali Ramadoss ,  David I. Standring ,  Kritika Bala

IPC分类号： G06F9/46 ,  G06F15/16 ,  G06F7/38 ,  G06F9/48

CPC分类号： G06F9/4881 ,  Y02D10/24

摘要： A computing device for performing scheduling operations for graphics hardware is described herein. The computing device includes a central processing unit (CPU) that is configured to execute an application. The computing device also includes a graphics scheduler configured to operate independently of the CPU. The graphics scheduler is configured to receive work queues relating to workloads from the application that are to execute on the CPU and perform scheduling operations for any of a number of graphics engines based on the work queues.

摘要翻译： 本文描述了用于执行图形硬件的调度操作的计算设备。 计算设备包括被配置为执行应用的中央处理单元（CPU）。 计算设备还包括被配置为独立于CPU操作的图形调度器。 图形调度器被配置为接收与在CPU上执行的应用程序的工作负载有关的工作队列，并且基于工作队列对多个图形引擎中的任何一个执行调度操作。