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    EFFICIENT HARDWARE MECHANISM TO ENSURE SHARED RESOURCE DATA COHERENCY ACROSS DRAW CALLS
    1.
    发明申请
    EFFICIENT HARDWARE MECHANISM TO ENSURE SHARED RESOURCE DATA COHERENCY ACROSS DRAW CALLS 有权
    有效的硬件机制，以确保共享资源数据的相似性

    公开(公告)号：US20150379661A1

    公开(公告)日：2015-12-31

    申请号：US14315597

    申请日：2014-06-26

    申请人： PRASOONKUMAR SURTI ,  ADITYA NAVALE ,  JEFFERY S. BOLES

    发明人： PRASOONKUMAR SURTI ,  ADITYA NAVALE ,  JEFFERY S. BOLES

    IPC分类号： G06T1/20 ,  G09G5/10 ,  G06T1/60 ,  G06T15/80

    CPC分类号： G06T1/20 ,  G06T15/005 ,  G09G5/363 ,  G09G2360/08

    摘要： Systems and methods may provide for receiving a plurality of signals from a software module associated with a shared resource such as, for example, an unordered access view (UAV). The plurality of signals may include a first signal that indicates whether a draw call accesses the shared resource, a second signal that indicates whether a boundary of the draw call has been reached, and a third signal that indicates whether the draw call has a coherency requirement. Additionally, a workload corresponding to the draw call may be selectively dispatched in a shader invocation based on the plurality of signals.

    摘要翻译： 系统和方法可以提供从与例如无序访问视图（UAV）等共享资源相关联的软件模块接收多个信号。 多个信号可以包括指示绘图呼叫是否访问共享资源的第一信号，指示绘制呼叫的边界是否已经到达的第二信号，以及指示绘制呼叫是否具有一致性要求的第三信号 。 此外，可以基于多个信号在着色器调用中选择性地调度与绘图调用相对应的工作量。

    Dynamic error handling using parity and redundant rows
    2.
    发明授权
    Dynamic error handling using parity and redundant rows 有权
    使用奇偶校验和冗余行的动态错误处理

    公开(公告)号：US09075741B2

    公开(公告)日：2015-07-07

    申请号：US13327845

    申请日：2011-12-16

    申请人： Altug Koker ,  Shailesh Shah ,  Aditya Navale ,  Murali Ramadoss ,  Satish K. Damaraju

    发明人： Altug Koker ,  Shailesh Shah ,  Aditya Navale ,  Murali Ramadoss ,  Satish K. Damaraju

    IPC分类号： G06F11/00 ,  G06F11/10 ,  H03M13/09 ,  H04L1/00 ,  H03M13/11

    CPC分类号： G06F11/1048 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1076 ,  H03M13/09 ,  H03M13/11 ,  H04L1/0057

    摘要： Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.

    摘要翻译： 公开了使用奇偶校验和冗余行的动态纠错的发明的实施例。 在一个实施例中，装置包括存储结构，奇偶校验逻辑，错误存储空间和错误事件发生器。 存储结构是存储多个数据值。 奇偶校验逻辑是检测存储在存储结构中的数据值中的奇偶校验错误。 错误存储空间是存储奇偶校验错误检测的指示。 错误事件发生器响应于存储在错误存储空间中的奇偶校验错误的指示而生成事件。

    METHOD AND APPARATUS FOR SUPPORTING PROGRAMMABLE SOFTWARE CONTEXT STATE EXECUTION DURING HARDWARE CONTEXT RESTORE FLOW
    3.
    发明申请
    METHOD AND APPARATUS FOR SUPPORTING PROGRAMMABLE SOFTWARE CONTEXT STATE EXECUTION DURING HARDWARE CONTEXT RESTORE FLOW 有权
    在硬件上下文恢复流程期间支持可编程软件上下文执行的方法和装置

    公开(公告)号：US20150123980A1

    公开(公告)日：2015-05-07

    申请号：US14072622

    申请日：2013-11-05

    申请人： Hema Chand Nalluri ,  Jeffery S. Boles ,  Murali Ramadoss ,  Aditya Navale ,  Lalit K. Saptarshi

    发明人： Hema Chand Nalluri ,  Jeffery S. Boles ,  Murali Ramadoss ,  Aditya Navale ,  Lalit K. Saptarshi

    IPC分类号： G06T15/00 ,  G06F9/46 ,  G06T1/20

    CPC分类号： G06F9/461 ,  G06T1/20

    摘要： A method and apparatus for supporting programmable software context state execution during hardware context restore flow is described. In one example, a context ID is assigned to graphics applications including a unique context memory buffer, a unique indirect context pointer and a corresponding size to each context ID, an indirect context offset, and an indirect context buffer address range. When execution of the first context workload is indirected, the state of the first context workload is saved to the assigned context memory buffer. The indirect context pointer, the indirect context offset and a size of the indirect context buffer address range are saved to registers that are independent of the saved context state. The context is restored by accessing the saved indirect context pointer, the indirect context offset and the buffer size.

    摘要翻译： 描述了用于在硬件上下文恢复流程期间支持可编程软件上下文状态执行的方法和装置。 在一个示例中，上下文ID被分配给包括唯一上下文存储器缓冲器，唯一间接上下文指针和对每个上下文ID，间接上下文偏移以及间接上下文缓冲器地址范围的对应大小的图形应用。 当第一上下文工作负载的执行被间接时，第一上下文工作负载的状态被保存到所分配的上下文存储器缓冲器中。 间接上下文指针，间接上下文偏移量和间接上下文缓冲区地址范围的大小保存到独立于保存的上下文状态的寄存器中。 通过访问保存的间接上下文指针，间接上下文偏移量和缓冲区大小来恢复上下文。

    MEMORY MAPPING FOR A GRAPHICS PROCESSING UNIT
    4.
    发明申请
    MEMORY MAPPING FOR A GRAPHICS PROCESSING UNIT 有权
    图形处理单元的存储映射

    公开(公告)号：US20140267323A1

    公开(公告)日：2014-09-18

    申请号：US13851400

    申请日：2013-03-27

    申请人： Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Aditya Navale

    发明人： Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Aditya Navale

    IPC分类号： G06T1/60

    CPC分类号： G06T1/60 ,  G06F9/485 ,  G06F12/1009 ,  G06F12/128 ,  G06T1/20

    摘要： An electronic device is described herein. The electronic device may include a page walker module to receive a page request of a graphics processing unit (GPU). The page walker module may detect a page fault associated with the page request. The electronic device may include a controller, at least partially comprising hardware logic. The controller is to monitor execution of the page request having the page fault. The controller determines whether to suspend execution of a work item at the GPU associated with the page request having the page fault, or to continue execution of the work item based on factors associated with the page request.

    摘要翻译： 本文描述了一种电子设备。 电子设备可以包括页面助行器模块，用于接收图形处理单元（GPU）的页面请求。 页面助行器模块可以检测与页面请求相关联的页面错误。 电子设备可以包括至少部分地包括硬件逻辑的控制器。 控制器将监视具有页面错误的页面请求的执行。 控制器确定是否在与具有页面错误的页面请求相关联的GPU处挂起工作项的执行，或者基于与页面请求相关联的因素来继续执行工作项。

    Method and apparatus for reordering memory requests for page coherency
    8.
    发明授权
    Method and apparatus for reordering memory requests for page coherency 有权
    用于重新排序页面一致性的存储器请求的方法和装置

    公开(公告)号：US07353349B2

    公开(公告)日：2008-04-01

    申请号：US11137700

    申请日：2005-05-24

    申请人： Jonathan B. Sadowsky ,  Aditya Navale

    发明人： Jonathan B. Sadowsky ,  Aditya Navale

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0859 ,  G06F12/0215

    摘要： A method and apparatus for reordering memory requests for page coherency. Various data streams are frequently found in separate areas of physical memory (i.e. each data stream is found in a separate memory “page”). Because these requests from different streams become intermixed, a certain amount of latency results from the resulting page “breaks.” These page breaks occur when consecutive requests are from different data streams, requiring accesses to different memory pages. When several separate streams of data are requested by a client, page coherency between requests diminishes. A reordering device regains lost page coherency, thereby reducing the amount of latency and increasing overall system performance.

    摘要翻译： 一种用于重新排序页面一致性的存储器请求的方法和装置。 经常在物理存储器的不同区域中找到各种数据流（即，每个数据流在单独的存储器“页面”中找到）。 因为来自不同流的这些请求被混合，所以产生的页面“断点”会导致一定量的延迟。 当连续的请求来自不同的数据流，需要访问不同的内存页时，会出现这些分页符。 当客户端请求几个单独的数据流时，请求之间的页面一致性减少。 重新排序设备恢复丢失页面一致性，从而减少延迟量并提高整体系统性能。