A low-pin-count non-volatile (NVM) memory with no more than two control signals that can at least program NVM cells, load data to be programmed into output registers, or read the NVM cells. At least one of the NVM cells has at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector is coupled to a second supply voltage line and having a select signal. At least one of the selected NVM cells can be coupled to at least one output register. No more than two control signals can be used to select the at least one NVM cells in the NVM sequentially for programming the data into the at least one NVM cells or loading data into the at least one output registers controlled by the pulse of the first signal and voltage level and/or timing of the second signal. Programming into the NVM cells, or loading data into output registers, can be determined by the voltage levels of the first to the second supply voltage lines. Reading at least one of the NVM cells can be activated by a third signal or by detecting ramping of the first or the second supply voltage line.