Invention Grant
- Patent Title: Non-volatile memory with vertical selection transistors
- Patent Title (中): 具有垂直选择晶体管的非易失性存储器
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Application No.: US14043718Application Date: 2013-10-01
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Publication No.: US09076878B2Publication Date: 2015-07-07
- Inventor: Francesco La Rosa , Stephan Niel , Arnaud Regnier , Yoann Goasduff
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Seed IP Law Group PLLC
- Priority: FR1259659 20121010
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/788 ; H01L29/66 ; G11C16/04 ; H01L27/115 ; H01L29/78 ; H01L29/417

Abstract:
The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.
Public/Granted literature
- US20140097481A1 NON-VOLATILE MEMORY WITH VERTICAL SELECTION TRANSISTORS Public/Granted day:2014-04-10
Information query
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