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    NON-VOLATILE MEMORY WITH VERTICAL SELECTION TRANSISTORS
    1.
    发明申请
    NON-VOLATILE MEMORY WITH VERTICAL SELECTION TRANSISTORS 有权
    具有垂直选择晶体管的非易失性存储器

    公开(公告)号：US20140097481A1

    公开(公告)日：2014-04-10

    申请号：US14043718

    申请日：2013-10-01

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Yoann Goasduff

    IPC: H01L29/788 ,  H01L29/66

    CPC classification number: H01L29/788 ,  G11C16/0433 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/4175 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827

    Abstract: The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.

    Abstract translation: 本公开涉及一种用于在半导体衬底上制造非易失性存储器的方法，包括以下步骤：在衬底的深度中注入形成选择晶体管的源极区的第一掺杂区，在衬底中形成掩埋栅，包括 在衬底的上表面和第一掺杂区之间延伸的深部分，埋入掩埋栅的两个相邻深部之间，形成一对存储单元的公共选择晶体管的公共漏极区的第二掺杂区，选择晶体管 因此具有在第一掺杂区域和第二掺杂区域之间延伸的沟道区域的一对存储单元，沿着与相邻两个深部分的两个掩埋栅极相对的面以及沿掩埋栅极的相对的上边缘注入，形成源极区域的第三掺杂区域 的电荷累积晶体管。

    METHOD FOR PRODUCING A PATTERN IN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT
    3.
    发明申请
    METHOD FOR PRODUCING A PATTERN IN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT 有权
    在集成电路和相关集成电路中生成图案的方法

    公开(公告)号：US20150037966A1

    公开(公告)日：2015-02-05

    申请号：US14451161

    申请日：2014-08-04

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Yoann Goasduff ,  Abderrezak Marzaki

    IPC: H01L21/308 ,  H01L21/266

    CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/3081 ,  H01L21/3085

    Abstract: At least one projecting block is formed in an element. The projecting block is then covered with a first cover layer so as to form a concave ridge self-aligned with the projecting block and having its concavity face towards the projecting block. A first trench is then formed in the ridge in a manner that is self-aligned with both the ridge and the projecting block. The first trench extends to a depth which reaches the projecting block. The projecting block is etched using the ridge and first trench as an etching mask to form a second trench in the projecting block that is self-aligned with the first trench. A pattern is thus produced by the second trench and unetched parts of the projecting block which delimit the second trench.

    Abstract translation: 在元件中形成至少一个突出块。 突出的块然后被第一覆盖层覆盖，以形成与突出块自对准的凹脊，并且其凹面朝向突出块。 然后以与脊和突出块两者自对准的方式在脊中形成第一沟槽。 第一沟槽延伸到到达突出块的深度。 使用脊和第一沟槽蚀刻突出块作为蚀刻掩模，以在与第一沟槽自对准的突出块中形成第二沟槽。 因此，通过限定第二沟槽的突出块的第二沟槽和未蚀刻部分产生图案。

    Non-volatile memory with vertical selection transistors
    6.
    发明授权
    Non-volatile memory with vertical selection transistors 有权
    具有垂直选择晶体管的非易失性存储器

    公开(公告)号：US09076878B2

    公开(公告)日：2015-07-07

    申请号：US14043718

    申请日：2013-10-01

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Yoann Goasduff

    IPC: H01L21/336 ,  H01L29/788 ,  H01L29/66 ,  G11C16/04 ,  H01L27/115 ,  H01L29/78 ,  H01L29/417

    CPC classification number: H01L29/788 ,  G11C16/0433 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/4175 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827

    Abstract: The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.

    Abstract translation: 本公开涉及一种用于在半导体衬底上制造非易失性存储器的方法，包括以下步骤：在衬底的深度中注入形成选择晶体管的源极区的第一掺杂区，在衬底中形成掩埋栅，包括 在衬底的上表面和第一掺杂区之间延伸的深部分，埋入掩埋栅的两个相邻深部之间，形成一对存储单元的公共选择晶体管的公共漏极区的第二掺杂区，选择晶体管 因此具有在第一掺杂区域和第二掺杂区域之间延伸的沟道区域的一对存储单元，沿着与相邻两个深部分的两个掩埋栅极相对的面以及沿掩埋栅极的相对的上边缘注入，形成源极区域的第三掺杂区域 的电荷累积晶体管。

    Method for producing a pattern in an integrated circuit and corresponding integrated circuit
    9.
    发明授权
    Method for producing a pattern in an integrated circuit and corresponding integrated circuit 有权
    用于在集成电路中生成图案的方法和相应的集成电路

    公开(公告)号：US09472413B2

    公开(公告)日：2016-10-18

    申请号：US14451161

    申请日：2014-08-04

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Yoann Goasduff ,  Abderrezak Marzaki

    IPC: H01L21/302 ,  H01L21/76 ,  H01L21/308 ,  H01L21/266 ,  H01L21/033

    CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/3081 ,  H01L21/3085

    Abstract: At least one projecting block is formed in an element. The projecting block is then covered with a first cover layer so as to form a concave ridge self-aligned with the projecting block and having its concavity face towards the projecting block. A first trench is then formed in the ridge in a manner that is self-aligned with both the ridge and the projecting block. The first trench extends to a depth which reaches the projecting block. The projecting block is etched using the ridge and first trench as an etching mask to form a second trench in the projecting block that is self-aligned with the first trench. A pattern is thus produced by the second trench and unetched parts of the projecting block which delimit the second trench.

    Abstract translation: 在元件中形成至少一个突出块。 突出的块然后被第一覆盖层覆盖，以形成与突出块自对准的凹脊，并且其凹面朝向突出块。 然后以与脊和突出块两者自对准的方式在脊中形成第一沟槽。 第一沟槽延伸到到达突出块的深度。 使用脊和第一沟槽蚀刻突出块作为蚀刻掩模，以在与第一沟槽自对准的突出块中形成第二沟槽。 因此，通过限定第二沟槽的突出块的第二沟槽和未蚀刻部分产生图案。

    Nonvolatile memory cells with a vertical selection gate of variable depth
    10.
    发明授权
    Nonvolatile memory cells with a vertical selection gate of variable depth 有权
    具有可变深度的垂直选择栅极的非易失性存储单元

    公开(公告)号：US08901634B2

    公开(公告)日：2014-12-02

    申请号：US13786213

    申请日：2013-03-05

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Yoann Goasduff ,  Stephan Niel ,  Arnaud Regnier

    IPC: H01L29/788 ,  G11C16/04 ,  H01L29/66 ,  H01L27/115

    CPC classification number: H01L29/7889 ,  G11C16/0425 ,  G11C16/0483 ,  G11C16/14 ,  H01L27/11524 ,  H01L29/66825

    Abstract: The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line.

    Abstract translation: 本公开涉及一种集成电路，其包括形成在半导体衬底中的至少两个存储单元和与存储单元的选择晶体管共同的掩埋栅极。 掩埋栅极具有在选择晶体管的垂直沟道区域的前面延伸的第一深度的第一部分，以及大于深入埋入源极线的第一深度的至少第二深度的第二部分。 掩埋栅极的下侧由形成选择晶体管的源极区域的掺杂区域界定，并且在埋入栅极的第二部分穿入埋入源极线的水平面到达掩埋源极线，由此源极区域 耦合到埋地源线。

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