Invention Grant
- Patent Title: Method of manufacturing and testing a chip package
- Patent Title (中): 制造和测试芯片封装的方法
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Application No.: US13745550Application Date: 2013-01-18
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Publication No.: US09082644B2Publication Date: 2015-07-14
- Inventor: Peter Ossimitz , Matthias von Daak , Gottfried Beer
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/66
- IPC: H01L21/66 ; G01R31/28

Abstract:
A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip. Further, the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which external terminal pads of the chip package are arranged. After production, the package is subjected to a package-level burn-in test.
Public/Granted literature
- US20140206109A1 Method of Manufacturing and Testing a Chip Package Public/Granted day:2014-07-24
Information query
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