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    Semiconductor chip having a dense arrangement of contact terminals
    1.
    发明授权
    Semiconductor chip having a dense arrangement of contact terminals 有权

    公开(公告)号：US10090251B2

    公开(公告)日：2018-10-02

    申请号：US14808798

    申请日：2015-07-24

    Applicant: Infineon Technologies AG

    Inventor： Peter Ossimitz ,  Gottfried Beer ,  Juergen Hoegerl ,  Andreas Munding

    IPC: H01L23/538 ,  H01L23/00 ,  H01L21/66

    Abstract: A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.

    Semiconductor Device Having a Chip Under Package
    3.
    发明申请
    Semiconductor Device Having a Chip Under Package 有权
    具有芯片封装的半导体器件

    公开(公告)号：US20160225745A1

    公开(公告)日：2016-08-04

    申请号：US15012086

    申请日：2016-02-01

    Applicant: Infineon Technologies AG

    Inventor： Gottfried Beer ,  Peter Ossimitz

    IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00

    CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/19104

    Abstract: A semiconductor device package includes an electronic component and an electrical interconnect. The electronic component is attached to the electrical interconnect. The electrical interconnect is configured to electrically couple the electronic component to external terminals of the semiconductor device package. The electrical interconnect has a first main face facing the electronic component and a second main face opposite the first main face. The semiconductor device package further includes a first semiconductor chip facing the second main face of the electrical interconnect.

    Abstract translation: 半导体器件封装包括电子元件和电互连。 电子部件附接到电互连。 电互连被配置为将电子部件电耦合到半导体器件封装的外部端子。 电互连具有面向电子部件的第一主面和与第一主面相对的第二主面。 半导体器件封装还包括面对电互连的第二主面的第一半导体芯片。

    Method of manufacturing and testing a chip package
    6.
    发明授权
    Method of manufacturing and testing a chip package 有权
    制造和测试芯片封装的方法

    公开(公告)号：US09082644B2

    公开(公告)日：2015-07-14

    申请号：US13745550

    申请日：2013-01-18

    Applicant: Infineon Technologies AG

    Inventor： Peter Ossimitz ,  Matthias von Daak ,  Gottfried Beer

    IPC: H01L21/66 ,  G01R31/28

    CPC classification number: H01L22/10 ,  G01R31/2884 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00014

    Abstract: A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip. Further, the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which external terminal pads of the chip package are arranged. After production, the package is subjected to a package-level burn-in test.

    Abstract translation: 描述了制造和测试芯片封装的方法。 要制造的芯片封装包括一个包含集成电路的半导体芯片和一个附着在半导体芯片上的加强结构。 此外，芯片封装具有与下主面相对的下主面和上主面，其中下主面至少部分地由半导体芯片的暴露表面形成，并且上主面由终端形成 所述加强结构的表面布置有所述芯片封装的外部端子焊盘。 生产后，对包装进行封装级老化测试。

    Chip Package Having Terminal Pads of Different Form Factors
    7.
    发明申请
    Chip Package Having Terminal Pads of Different Form Factors 有权
    芯片封装具有不同形状因子的端子板

    公开(公告)号：US20140203278A1

    公开(公告)日：2014-07-24

    申请号：US13745537

    申请日：2013-01-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Peter Ossimitz

    IPC: H01L21/66

    CPC classification number: H01L22/32 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014

    Abstract: A chip package includes an integrated circuit chip. A first group of terminal pads of the chip package is electrically connected to the integrated circuit chip and a second group of terminal pads of the chip package is electrically connected to the integrated circuit chip. The first and second groups of terminal pads are arranged on a common terminal surface of the chip package. A pad size of a terminal pad of the first group of terminal pads is greater than a pad size of a terminal pad of the second group of terminal pads.

    Abstract translation: 芯片封装包括集成电路芯片。 芯片封装的第一组端子焊盘电连接到集成电路芯片，并且芯片封装的第二组端子焊盘电连接到集成电路芯片。 第一和第二组端子焊盘被布置在芯片封装的公共端子表面上。 第一组端子焊盘的端子焊盘的焊盘尺寸大于第二组端子焊盘的端子焊盘的焊盘尺寸。

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