Invention Grant
US09110829B2 MRAM smart bit write algorithm with error correction parity bits
有权
具有纠错奇偶校验位的MRAM智能位写入算法
- Patent Title: MRAM smart bit write algorithm with error correction parity bits
- Patent Title (中): 具有纠错奇偶校验位的MRAM智能位写入算法
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Application No.: US13917772Application Date: 2013-06-14
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Publication No.: US09110829B2Publication Date: 2015-08-18
- Inventor: Yue-Der Chih , Hung-Chang Yu , Kai-Chun Lin , Chin-Yi Huang , Laun C. Tran
- Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: G11C29/00
- IPC: G11C29/00 ; H03M13/00 ; G06F11/10 ; G06F11/14 ; G11C11/16 ; G11C13/00

Abstract:
Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location.
Public/Granted literature
- US20140157088A1 MRAM Smart Bit Write Algorithm with Error Correction Parity Bits Public/Granted day:2014-06-05
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