公开(公告)号：US20150355963A1

公开(公告)日：2015-12-10

申请号：US14827591

申请日：2015-08-17

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yue-Der Chih ,  Hung-Chang Yu ,  Kai-Chun Lin ,  Chin-Yi Huang ,  Laun C. Tran

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11

CPC classification number: G06F11/1056 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1048 ,  G06F11/1052 ,  G06F11/1402 ,  G06F11/141 ,  G11C11/1675 ,  G11C11/1677 ,  G11C2013/0076 ,  H03M13/11 ,  H03M13/611

Abstract: Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.

Abstract translation: 一些实施例涉及包括写入电路，读取电路和比较电路的系统。 写电路被配置为尝试将期望的多位字写入存储器件中的存储器位置。 读取电路被配置为从存储器位置读取实际的多位字。 比较电路被配置为将从存储器位置读取的实际多位字与预先写入存储器位置的预期多位字进行比较，以区分实际多位字中的多个错误位和 实际多位字中正确位数。 写电路还被配置为将错误位的数量重写到存储器位置，而不尝试将正确位的数量重写到存储器位置。

公开(公告)号：US09747159B2

公开(公告)日：2017-08-29

申请号：US14827591

申请日：2015-08-17

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yue-Der Chih ,  Hung-Chang Yu ,  Kai-Chun Lin ,  Chin-Yi Huang ,  Laun C. Tran

IPC: G11C29/00 ,  H03M13/00 ,  G06F11/10 ,  H03M13/11 ,  G06F11/14 ,  G11C11/16 ,  G11C13/00

CPC classification number: G06F11/1056 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1048 ,  G06F11/1052 ,  G06F11/1402 ,  G06F11/141 ,  G11C11/1675 ,  G11C11/1677 ,  G11C2013/0076 ,  H03M13/11 ,  H03M13/611

Abstract: Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.

公开(公告)号：US09110829B2

公开(公告)日：2015-08-18

申请号：US13917772

申请日：2013-06-14

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yue-Der Chih ,  Hung-Chang Yu ,  Kai-Chun Lin ,  Chin-Yi Huang ,  Laun C. Tran

IPC: G11C29/00 ,  H03M13/00 ,  G06F11/10 ,  G06F11/14 ,  G11C11/16 ,  G11C13/00

CPC classification number: G06F11/1056 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1048 ,  G06F11/1052 ,  G06F11/1402 ,  G06F11/141 ,  G11C11/1675 ,  G11C11/1677 ,  G11C2013/0076 ,  H03M13/11 ,  H03M13/611

Abstract: Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location.

Abstract translation: 本公开的一些方面涉及一种方法。 该方法尝试将期望的多位字写入存储器中的存储器位置。 在尝试写入多位字之后，从存储器位置读取实际的多位字。 然后将实际的多位字与期望的多位字进行比较，以识别存储在存储器位置中的错误位数和数量的正确位。 错误位的数量被重写到存储器位置，而不尝试将正确的位重写到存储器位置。

公开(公告)号：US20140157088A1

公开(公告)日：2014-06-05

申请号：US13917772

申请日：2013-06-14

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yue-Der Chih ,  Hung-Chang Yu ,  Kai-Chun Lin ,  Chin-Yi Huang ,  Laun C. Tran

IPC: G06F11/10 ,  G06F11/14

CPC classification number: G06F11/1056 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1048 ,  G06F11/1052 ,  G06F11/1402 ,  G06F11/141 ,  G11C11/1675 ,  G11C11/1677 ,  G11C2013/0076 ,  H03M13/11 ,  H03M13/611

Abstract: Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location.

Abstract translation: 本公开的一些方面涉及一种方法。 该方法尝试将期望的多位字写入存储器中的存储器位置。 在尝试写入多位字之后，从存储器位置读取实际的多位字。 然后将实际的多位字与期望的多位字进行比较，以识别存储在存储器位置中的错误位数和数量的正确位。 错误位的数量被重写到存储器位置，而不尝试将正确的位重写到存储器位置。