Invention Grant
US09117492B2 Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits
有权
用于调整具有寻址和相邻位的存储单元的漏极偏置的方法和装置
- Patent Title: Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits
- Patent Title (中): 用于调整具有寻址和相邻位的存储单元的漏极偏置的方法和装置
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Application No.: US14556973Application Date: 2014-12-01
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Publication No.: US09117492B2Publication Date: 2015-08-25
- Inventor: Han-Sung Chen , Chung-Kuang Chen , Chun-Hsiung Hung
- Applicant: Macronix International Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Kenta Suzue
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C7/22 ; G11C11/56

Abstract:
The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.
Public/Granted literature
- US20150085588A1 METHOD AND APPARATUS FOR ADJUSTING DRAIN BIAS OF A MEMORY CELL WITH ADDRESSED AND NEIGHBOR BITS Public/Granted day:2015-03-26
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