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公开(公告)号：US20230317121A1
公开(公告)日：2023-10-05
申请号：US17709174
申请日：2022-03-30
发明人： Chung-Kuang Chen , Tzeng-Huei Shiau
IPC分类号： G11C5/14 , G11C5/06 , H01L23/522 , H01L23/528
CPC分类号： G11C5/145 , G11C5/147 , G11C5/063 , H01L23/5223 , H01L23/528
摘要： A capacitor string structure, a memory device and a charge pump circuit thereof are provided. The capacitor string structure includes a plurality of conductive plates. The conductive plates are disposed in the memory device. The conductive plates are stacked to each other, and respectively form a plurality of word lines of the memory device, where two neighbored conductive plates form a capacitor.
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公开(公告)号：US10790009B1
公开(公告)日：2020-09-29
申请号：US16552153
申请日：2019-08-27
发明人： Chung-Kuang Chen , Han-Sung Chen
IPC分类号： G11C7/12 , G11C11/4091 , G11C7/10 , G11C11/4074 , G11C11/4094
摘要： A memory device comprises a memory cell array, a plurality of sense amplifiers and a memory controller for controlling the plurality of sense amplifiers. The memory cell array includes a plurality of bit lines, where a bit line is coupled to a plurality of memory cells. A sense amplifier is coupled to a bit line and provides a sensing current to access data from one or more memory cells of the plurality of memory cells corresponding to the bit line. The memory controller performs operations comprising: during a pre-charging stage of a memory access cycle, providing, to a particular sense amplifier, a first voltage; and during a sensing stage of the memory access cycle, providing, to the particular sense amplifier, a second voltage, where the second voltage is a non-zero voltage that is lower than the first voltage.
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公开(公告)号：US09270272B2
公开(公告)日：2016-02-23
申请号：US14467419
申请日：2014-08-25
IPC分类号： G06F1/12 , G06F1/00 , G06F1/04 , G06F3/02 , G06F3/16 , H03B5/32 , H03K19/0175 , G06F1/08 , G05F3/02 , H03L5/00 , G06F1/10
CPC分类号： H03K19/018528 , G05F3/02 , G06F1/04 , G06F1/08 , G06F1/10 , G06F1/12 , H03K19/0175 , H03L5/00
摘要： The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.
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公开(公告)号：US20160042794A1
公开(公告)日：2016-02-11
申请号：US14454510
申请日：2014-08-07
IPC分类号： G11C16/08 , H03K19/0175
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10 , H03K19/017509
摘要： A level shifter receiving an input with a relatively narrow voltage range and provides an output with a relatively wide voltage range. The level shifter including a transistor with a turn-on voltage. Control circuitry applies a bias to the level shifter such that the transistor does not receive the turn-on voltage.
摘要翻译： 电平移位器接收具有相对窄的电压范围的输入并提供具有相对宽的电压范围的输出。 电平移位器包括具有导通电压的晶体管。 控制电路向电平移位器施加偏置，使得晶体管不接收导通电压。
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公开(公告)号：US09191003B2
公开(公告)日：2015-11-17
申请号：US14071790
申请日：2013-11-05
发明人： Chung-Kuang Chen
IPC分类号： H03K19/017 , H03K19/00 , H03K19/0175
CPC分类号： H03K19/017509 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , H03K19/0005 , H03K19/017
摘要： An integrated circuit of a memory is provided. The integrated circuit comprises a first data driving circuit and a transmitting transistor. The first data driving circuit outputs a first data voltage to a first node. The transmitting transistor is coupled between the first node and a second node. When the transmitting transistor receives a bias voltage and the voltage level of the first node is a first voltage level, the transmitting transistor makes the voltage level of the second node to be set as a third voltage level, third voltage level is close to or substantially equal to the first voltage level. When the transmitting transistor receives the bias voltage and the voltage level of the first node is the second voltage level, the voltage level of the second node is independently of the voltage level of the first node.
摘要翻译： 提供存储器的集成电路。 集成电路包括第一数据驱动电路和发送晶体管。 第一数据驱动电路将第一数据电压输出到第一节点。 发射晶体管耦合在第一节点和第二节点之间。 当发送晶体管接收到偏置电压并且第一节点的电压电平为第一电压电平时，发送晶体管将第二节点的电压电平设置为第三电压电平，第三电压电平接近或基本上 等于第一个电压电平。 当发射晶体管接收偏置电压并且第一节点的电压电平是第二电压电平时，第二节点的电压电平独立于第一节点的电压电平。
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公开(公告)号：US08830754B2
公开(公告)日：2014-09-09
申请号：US13959780
申请日：2013-08-06
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/32
摘要： A memory access method is applied in a memory controller for accessing a memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes: enabling the string select signal and disabling the string select signal before a read phase.
摘要翻译： 存储器访问方法应用于存储器控制器中，用于访问存储器阵列，包括由字符串选择信号全局控制的多个相应的选择开关。 存储器访问方法包括：在读取阶段之前启用字符串选择信号并禁用字符串选择信号。
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公开(公告)号：US12061125B2
公开(公告)日：2024-08-13
申请号：US17011864
申请日：2020-09-03
发明人： Chia-Ming Hu , Chung-Kuang Chen , Chia-Ching Li , Chien-Fu Huang
摘要： An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a reference circuit that generates a first reference with a first non-zero temperature coefficient and a second reference with a second temperature coefficient having a different magnitude than the first non-zero temperature coefficient. A detector circuit on the integrated circuit, having temperature and process variation compensation, converts a difference between the first and second references into a digital signal indicating temperature on the integrated circuit.
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公开(公告)号：US11842789B2
公开(公告)日：2023-12-12
申请号：US17709174
申请日：2022-03-30
发明人： Chung-Kuang Chen , Tzeng-Huei Shiau
IPC分类号： G11C5/14 , H01L23/528 , H01L23/522 , G11C5/06
CPC分类号： G11C5/145 , G11C5/063 , G11C5/147 , H01L23/528 , H01L23/5223
摘要： A capacitor string structure, a memory device and a charge pump circuit thereof are provided. The capacitor string structure includes a plurality of conductive plates. The conductive plates are disposed in the memory device. The conductive plates are stacked to each other, and respectively form a plurality of word lines of the memory device, where two neighbored conductive plates form a capacitor.
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公开(公告)号：US11710763B2
公开(公告)日：2023-07-25
申请号：US17471216
申请日：2021-09-10
发明人： Chung-Kuang Chen , Chia-Ching Li , Chien-Fu Huang , Chia-Ming Hu
CPC分类号： H01L28/86 , H01G4/012 , H01G4/232 , H01G4/30 , H01G4/33 , H01G4/38 , H01L23/5222 , H01L23/5223 , H01L27/0629
摘要： A metal capacitor provided includes a first metal layer and a second metal layer disposed above a substrate. The first metal layer includes a first electrode sheet and a second electrode sheet, and the second metal layer includes a third electrode sheet and a fourth electrode sheet. The first electrode sheet and the second electrode sheet collectively form a first coplanar capacitor. The third electrode sheet and the fourth electrode sheet collectively form a second coplanar capacitor. At least a portion of the fourth electrode sheet is arranged above the first electrode sheet, and the first electrode sheet and the fourth electrode sheet collectively form a first vertical capacitor. At least a portion of the third electrode sheet is arranged above the second electrode sheet, and the second electrode sheet and the third electrode sheet collectively form a second vertical capacitor.
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公开(公告)号：US11626864B1
公开(公告)日：2023-04-11
申请号：US17545942
申请日：2021-12-08
发明人： Chung-Kuang Chen
IPC分类号： H03K19/0175 , H03K19/0185 , G11C7/00 , H03K3/356
摘要： A level shifter circuit to convert a first signal having an input voltage range V1 to a level shifted output having an output voltage range V2 includes an NMOS depletion mode transistor having a drain terminal connected to an output range upper-level supply node, a source connected to an intermediate node and a gate connected to an output node, a PMOS enhancement mode transistor having a drain terminal connected to the output node, a source connected to the intermediate node and a gate connected to an input node, and an NMOS enhancement mode transistor having a drain terminal connected to the output node, a source connected to an output range lower-level supply node and a gate connected to the input node.
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