公开(公告)号：US12131772B2

公开(公告)日：2024-10-29

申请号：US17751445

申请日：2022-05-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Shang-Chi Yang ,  Fu-Nian Liang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G11C16/00 ,  G11C5/06 ,  G11C11/4072 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4094 ,  G11C5/063 ,  G11C11/4072 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

Abstract: A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

公开(公告)号：US12094569B2

公开(公告)日：2024-09-17

申请号：US17694313

申请日：2022-03-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Chung-Kuang Chen ,  Chun-Hsiung Hung

IPC: G11C7/18

CPC classification number: G11C7/18 ,  G11C2207/005

Abstract: A three-dimensional memory structure is provided and including a memory array, including a first and a second sub-arrays, each having a first selection line, plural word lines, and a second selection line; a connection structure, including plural connection areas, and at least one of extension structures of the first selection line, the plural of word lines, and the second selection line is coupled to a corresponding connection area of the plurality of connection areas; a pass gate set, arranged under the connection structure and between the first and the second sub-arrays, the pass gate set including plural pass gates, and, the word lines and the second selection line, and the pass gates are respectively coupled to the corresponding connection areas; and a drive circuit, coupled to the pass gate set, and disposed under the connection structure.

公开(公告)号：US11984371B2

公开(公告)日：2024-05-14

申请号：US18341957

申请日：2023-06-27

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Su-Chueh Lo

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L22/32 ,  G01R31/2896 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/1623

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. In one aspect, a chiplet system includes multiple integrated circuit devices electrically connected together. The integrated circuit devices include an integrated circuit device including: an integrated circuit, a plurality of first type bonding pads electrically connected to the integrated circuit and electrically connected to at least one other of the integrated circuit devices, and one or more second type bonding pads electrically isolated from the at least one other of the integrated circuit devices. At least one of the plurality of first type bonding pads is configured to be electrically connected to a corresponding one of the one or more second type bonding pads.

公开(公告)号：US11842769B2

公开(公告)日：2023-12-12

申请号：US17721207

申请日：2022-04-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Tien-Yen Wang ,  Yun-Chen Chou ,  Chun-Hsiung Hung

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: At least one embodiment of the disclosure is directed to a memory circuit having a leakage current blocking mechanism and a memory device having the memory circuit. In an aspect, one embodiment of the disclosure describes a memory circuit which includes not limited to a memory array which includes a first memory cell connected to a first bit line and a second memory cell connected to a second bit line, a pre-charge circuit which is connected to the memory array and includes a first pre-charge device, and a programming circuit which is connected to the pre-charge circuit and comprises a programming transistor which has a higher drive capability than the first pre-charge device so as to drive the first bit line to a ground voltage in response to the first write operation, wherein in response to a first write operation on the first memory cell, a current flow exists between the programming circuit and the first pre-charge device.

公开(公告)号：US20230343657A1

公开(公告)日：2023-10-26

申请号：US18341957

申请日：2023-06-27

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Su-Chueh Lo

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/2896 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/1623

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. In one aspect, a chiplet system includes multiple integrated circuit devices electrically connected together. The integrated circuit devices include an integrated circuit device including: an integrated circuit, a plurality of first type bonding pads electrically connected to the integrated circuit and electrically connected to at least one other of the integrated circuit devices, and one or more second type bonding pads electrically isolated from the at least one other of the integrated circuit devices. At least one of the plurality of first type bonding pads is configured to be electrically connected to a corresponding one of the one or more second type bonding pads.

公开(公告)号：US11217316B2

公开(公告)日：2022-01-04

申请号：US17008746

申请日：2020-09-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung

IPC: G11C16/06 ,  G11C16/26 ,  G11C11/56 ,  G11C16/30 ,  G11C16/08 ,  G11C16/04

Abstract: A sensing circuit, a sensing method and a memory device are provided. The sensing method is applied to the memory device having the sensing circuit. The sensing circuit includes a compensation source and a sensing module. The compensation source is capable of providing a compensating current to a first node during a read cycle. The sensing module is coupled to the first node. A cell of the memory device is coupled to the first node. The cell is capable of generating a cell current during the read cycle, and the sensing module determines that the cell is in a first storing state or a second storing state in response to a relationship between the compensating current and the cell current.

公开(公告)号：US20210366793A1

公开(公告)日：2021-11-25

申请号：US16877697

申请日：2020-05-19

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Su-Chueh Lo

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/00 ,  H01L23/498

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. An example integrated circuit device includes an integrated circuit, first type bonding pads and second type bonding pads. Each of the first type bonding pads is electrically connected to the integrated circuit and configured to be electrically connected to a corresponding external integrated circuit device. Each of the second type bonding pads is configured to have no electrical connection with the corresponding external integrated circuit device. Each of the first type bonding pads is configured to be electrically connected to a corresponding one of the second type bonding pads. A number of the first type bonding pads can be larger than a number of the second type bonding pads. Each of the second type bonding pads can have a larger pad area for probing than each of the first type bonding pads.

公开(公告)号：US10290364B2

公开(公告)日：2019-05-14

申请号：US14849412

申请日：2015-09-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung ,  Chi Lo ,  Chun-Hsiung Hung

IPC: G11C29/04 ,  G11C29/00

Abstract: An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.

公开(公告)号：US09940048B2

公开(公告)日：2018-04-10

申请号：US14310502

申请日：2014-06-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Su-Chueh Lo

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/14

CPC classification number: G06F3/0622 ,  G06F3/062 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/1416

Abstract: Methods for protecting data on an integrated circuit including a memory are described. One method includes storing nonvolatile protection codes on the integrated circuit. The nonvolatile protection codes have a first value indicating a protected state or a second value indicating an unprotected state for respective sectors in a plurality of sectors of the memory. The method includes storing volatile protection codes on the integrated circuit. The volatile protection codes have a first value indicating a protected state or a second value indicating an unprotected state for respective sectors in the plurality of sectors. The method includes blocking modification in a particular sector using circuitry on the integrated circuit when the volatile protection code for the particular sector has the first value, else allowing modification in the particular sector, and setting the volatile protection codes to values of the nonvolatile protection codes in an initialization procedure.

公开(公告)号：US09933977B1

公开(公告)日：2018-04-03

申请号：US15346790

申请日：2016-11-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Han-Sung Chen ,  Chung-Kuang Chen

IPC: G11C7/00 ,  G06F3/06 ,  G11C16/34 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/3431 ,  G11C16/3495

Abstract: A memory device includes a memory unit including a plurality of memory cells, and a controller including a storage unit that stores a plurality of operation selections each corresponding to a property of at least one selected memory cell among the plurality of memory cells.