For certain three dimensionally stacked memory devices, bit lines or word lines for memory cells are stacked in spaced apart ridge like structures arranged to extend in a first direction. In such structures, complementary wordlines or bit lines, can be damascene features between the spaced apart. The damascene conductors can be formed using double patterned masks to etch sub-lithographic sacrificial lines, forming a fill over the sacrificial lines, and then removing the sacrificial lines to leave trenches that act as the damascene molds in the fill. Then the trenches are filled with the conductor material. The 3D memory array can include dielectric charge trapping memory cells, which have a high-K blocking dielectric layer, and in which the conductor material comprises a high work function material.