A resistive memory array includes a controller, a test reset driver coupled to the controller, a test write driver also coupled to the controller, and a test read sense amplifier also coupled to the controller. The resistive memory array also includes a set of test resistive memory elements representing a resistive memory macro. The test resistive memory elements are coupled to the test reset driver, the test write driver and the test read sense amplifier. A change in the state of one of the test resistive memory elements represents a change in the state of a set of corresponding elements in the resistive memory macro.