Invention Grant
- Patent Title: 3D semiconductor device and structure with back-bias
- Patent Title (中): 3D半导体器件和具有背偏的结构
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Application No.: US13492395Application Date: 2012-06-08
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Publication No.: US09136153B2Publication Date: 2015-09-15
- Inventor: Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Ze'ev Wurman , Paul Lim
- Applicant: Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Ze'ev Wurman , Paul Lim
- Applicant Address: US CA San Jose
- Assignee: MONOLITHIC 3D INC.
- Current Assignee: MONOLITHIC 3D INC.
- Current Assignee Address: US CA San Jose
- Agency: Tran & Associates
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L25/065 ; H01L21/683 ; H01L21/74 ; H01L21/762 ; H01L21/768 ; H01L21/822 ; H01L21/8238 ; H01L21/84 ; H01L23/48 ; H01L23/525 ; H01L27/02 ; H01L27/06 ; H01L27/092 ; H01L27/10 ; H01L27/105 ; H01L27/108 ; H01L27/11 ; H01L27/112 ; H01L27/115 ; H01L27/118 ; H01L27/12 ; H01L29/423 ; H01L29/66 ; H01L29/78 ; H01L29/788 ; H01L29/792 ; H01L23/367 ; H01L23/00

Abstract:
A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnection layer, and where at least one of the second transistors has a back-bias structure designed to modify the performance of at least one of the second transistors.
Public/Granted literature
- US20120248595A1 SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE Public/Granted day:2012-10-04
Information query
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