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US09136153B2 3D semiconductor device and structure with back-bias 有权
3D半导体器件和具有背偏的结构

3D semiconductor device and structure with back-bias
Abstract:
A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnection layer, and where at least one of the second transistors has a back-bias structure designed to modify the performance of at least one of the second transistors.
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